On 9/30/26 13:58, Khatri, Sunil wrote:
>
> On 30-09-2026 05:11 pm, Christian König wrote:
>> On 9/30/26 13:35, Khatri, Sunil wrote:
>>> On 30-09-2026 05:01 pm, Christian König wrote:
>>>> On 9/30/26 13:16, Sunil Khatri wrote:
>>>>> vmid_mask_gfxhub/vmid_mask_mmhub makes more sense logically in
>>>>> vm_manager than the mes ip struct.
>>>> That's the VMID mask for the user queues, so I would name it
>>>> vmid_mask_uq_gfxhub/vmid_mask_uq_mmhub.
>>>>
>>>> Apart from that looks good to me.
>>> Noted. Another point here if that is the case then should i change that in
>>> MES HW layer too..
>>> unionMESAPI_SET_HW_RESOURCES{
>>> struct{
>>> unionMES_API_HEADER header;
>>> uint32_t vmid_mask_mmhub;
>>> uint32_t vmid_mask_gfxhub;
>>>
>>> Should i update here too or this is fine ??
>> No, that is fine. The MES handles only user queues here so that is unambious.
>>
>> But thinking more about it, we should also do a bunch of more cleanups.
>>
>> The structure amdgpu_vmid_mgr is really the per VMHUB structure for example.
>>
>> And the vmid_mask in the that structure is really the mask of VMIDs used by
>> kernel queues.
>>
>> We should probably name that structure and the field more appropriate.
>>
>> Regards,
>> Christian.
>
> That's true.
> But since it is used by both GFXHUB as well as MMHUB so something generic
> seems ok to me. But we can change vmid_mask -> kernel_vmid_mask. Suggest if
> you still think to change the amdgpu_vmid_mgr to something else like
> amdgpu_vmhub_vmid_mgr or amdgpu_kernel_vmid_mgr... but these names seems
> pretty big.
Just name that amdgpu_vmhub instead.
And using kq and uq as accronyms for kernel and user queues seem pretty
staright forward to me.
Regards,
Christian.
>
> Regards
> Sunil Khatri
>
>>
>>> Regards
>>> Sunil Khatri
>>>
>>>> Regards,
>>>> Christian.
>>>>
>>>>> Signed-off-by: Sunil Khatri <[email protected]>
>>>>> ---
>>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 8 ++++----
>>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 2 --
>>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 4 ++++
>>>>> drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 4 ++--
>>>>> drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 4 ++--
>>>>> drivers/gpu/drm/amd/amdgpu/mes_v12_1.c | 4 ++--
>>>>> 6 files changed, 14 insertions(+), 12 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
>>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
>>>>> index 5285c1d1fd4cb..9c36ccf5d5659 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
>>>>> @@ -137,8 +137,8 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
>>>>> total_vmid_mask = (u32)((1UL << 16) - 1);
>>>>> reserved_vmid_mask = (u32)((1UL << adev->vm_manager.first_kfd_vmid)
>>>>> - 1);
>>>>> - adev->mes.vmid_mask_mmhub = 0xFF00;
>>>>> - adev->mes.vmid_mask_gfxhub = total_vmid_mask & ~reserved_vmid_mask;
>>>>> + adev->vm_manager.vmid_mask_mmhub = 0xFF00;
>>>>> + adev->vm_manager.vmid_mask_gfxhub = total_vmid_mask &
>>>>> ~reserved_vmid_mask;
>>>>> num_pipes = adev->gfx.me.num_pipe_per_me * adev->gfx.me.num_me;
>>>>> if (num_pipes > AMDGPU_MES_MAX_GFX_PIPES)
>>>>> @@ -184,8 +184,8 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
>>>>> dev_info(adev->dev,
>>>>> "MES: vmid_mask_mmhub 0x%08x, vmid_mask_gfxhub 0x%08x\n",
>>>>> - adev->mes.vmid_mask_mmhub,
>>>>> - adev->mes.vmid_mask_gfxhub);
>>>>> + adev->vm_manager.vmid_mask_mmhub,
>>>>> + adev->vm_manager.vmid_mask_gfxhub);
>>>>> dev_info(adev->dev,
>>>>> "MES: gfx_hqd_mask 0x%08x, compute_hqd_mask 0x%08x,
>>>>> sdma_hqd_mask 0x%08x\n",
>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
>>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
>>>>> index 594fb817e0a38..2b13a5b375393 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
>>>>> @@ -122,8 +122,6 @@ struct amdgpu_mes {
>>>>> void
>>>>> *mqd_backup[AMDGPU_MAX_MES_INST_PIPES];
>>>>> struct amdgpu_irq_src irq[AMDGPU_MAX_MES_INST_PIPES];
>>>>> - uint32_t vmid_mask_gfxhub;
>>>>> - uint32_t vmid_mask_mmhub;
>>>>> uint32_t
>>>>> gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];
>>>>> uint32_t
>>>>> compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES];
>>>>> uint32_t
>>>>> sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];
>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>>>>> index 98cdd7e3475fb..5f22c146e2339 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>>>>> @@ -413,6 +413,10 @@ struct amdgpu_vm_manager {
>>>>> /* Global registration of recent page fault information */
>>>>> struct amdgpu_vm_fault_info fault_info;
>>>>> unsigned int npa_vmid;
>>>>> +
>>>>> + /* VMID masks for GFXHUB and MMHUB */
>>>>> + uint32_t vmid_mask_gfxhub;
>>>>> + uint32_t vmid_mask_mmhub;
>>>>> };
>>>>> struct amdgpu_bo_va_mapping;
>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
>>>>> b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
>>>>> index d1cd665ab301c..178ef8dfe6d61 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
>>>>> @@ -1080,8 +1080,8 @@ static int mes_v11_0_set_hw_resources(struct
>>>>> amdgpu_mes *mes)
>>>>> mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC;
>>>>> mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
>>>>> - mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
>>>>> - mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
>>>>> + mes_set_hw_res_pkt.vmid_mask_mmhub =
>>>>> adev->vm_manager.vmid_mask_mmhub;
>>>>> + mes_set_hw_res_pkt.vmid_mask_gfxhub =
>>>>> adev->vm_manager.vmid_mask_gfxhub;
>>>>> mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
>>>>> mes_set_hw_res_pkt.paging_vmid = 0;
>>>>> mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr[0];
>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
>>>>> b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
>>>>> index c0719d8fa63e9..f2dd4323ffd3e 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
>>>>> @@ -1042,8 +1042,8 @@ static int mes_v12_0_set_hw_resources(struct
>>>>> amdgpu_mes *mes, int pipe)
>>>>> mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
>>>>> if (pipe == AMDGPU_MES_SCHED_PIPE) {
>>>>> - mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
>>>>> - mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
>>>>> + mes_set_hw_res_pkt.vmid_mask_mmhub =
>>>>> adev->vm_manager.vmid_mask_mmhub;
>>>>> + mes_set_hw_res_pkt.vmid_mask_gfxhub =
>>>>> adev->vm_manager.vmid_mask_gfxhub;
>>>>> mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
>>>>> mes_set_hw_res_pkt.paging_vmid = 0;
>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
>>>>> b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
>>>>> index 20159fb9d6ea3..c3e1f9a746ce0 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
>>>>> @@ -685,8 +685,8 @@ static int mes_v12_1_set_hw_resources(struct
>>>>> amdgpu_mes *mes,
>>>>> mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
>>>>> if (pipe == AMDGPU_MES_SCHED_PIPE) {
>>>>> - mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
>>>>> - mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
>>>>> + mes_set_hw_res_pkt.vmid_mask_mmhub =
>>>>> adev->vm_manager.vmid_mask_mmhub;
>>>>> + mes_set_hw_res_pkt.vmid_mask_gfxhub =
>>>>> adev->vm_manager.vmid_mask_gfxhub;
>>>>> mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
>>>>> mes_set_hw_res_pkt.paging_vmid = 0;
>>>>>
