From: Harry Wentland <[email protected]> On DCN4 the per-plane MCM shaper and 3D LUT state wasn't visible in the DTN log: dcn401 wired read_mpcc_state to mpc1_read_mpcc_state, which only reads the base MPCC blend registers, and the MPCC section didn't print the LUT fields even where they were populated.
Add mpc401_read_mpcc_state to also read MPCC_MCM_3DLUT_MODE (mode current and size) and MPCC_MCM_SHAPER_CONTROL (mode current), and print SHAPER, 3DLUT and 3DLUT_SIZE columns in the MPCC section. Mode is 0 bypass, 1 RAM_A, 2 RAM_B; 3DLUT_SIZE is 0 for 17x17x17 and 1 for 9x9x9. Assisted-by: Copilot:claude-opus-4.8 Reviewed-by: Alex Hung <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Roman Li <[email protected]> --- .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 6 +++--- .../drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c | 18 +++++++++++++++++- 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 884319b22cc1..33f7ab4c6c15 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -542,16 +542,16 @@ static void dcn10_log_color_state(struct dc *dc, dc->caps.color.dpp.ogam_ram, dc->caps.color.dpp.ocsc); - DTN_INFO("MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE\n"); + DTN_INFO("MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE SHAPER 3DLUT 3DLUT_SIZE\n"); for (i = 0; i < pool->mpcc_count; i++) { struct mpcc_state s = {0}; pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s); if (s.opp_id != 0xf) - DTN_INFO("[%2d]: %2xh %2xh %6xh %4d %10d %7d %12d %4d\n", + DTN_INFO("[%2d]: %2xh %2xh %6xh %4d %10d %7d %12d %4d %6d %5d %10d\n", i, s.opp_id, s.dpp_id, s.bot_mpcc_id, s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only, - s.idle); + s.idle, s.shaper_lut_mode, s.lut3d_mode, s.lut3d_size); } DTN_INFO("\n"); DTN_INFO("MPC Color Caps: gamut_remap:%d, 3dlut:%d, ogam_ram:%d, ocsc:%d\n\n", diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c index e59454090691..5f5c27eb1d64 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c @@ -627,8 +627,24 @@ void mpc401_get_lut_mode(struct mpc *mpc, } } +static void mpc401_read_mpcc_state( + struct mpc *mpc, + int mpcc_inst, + struct mpcc_state *s) +{ + struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc); + + mpc1_read_mpcc_state(mpc, mpcc_inst, s); + + REG_GET_2(MPCC_MCM_3DLUT_MODE[mpcc_inst], + MPCC_MCM_3DLUT_MODE_CURRENT, &s->lut3d_mode, + MPCC_MCM_3DLUT_SIZE, &s->lut3d_size); + REG_GET(MPCC_MCM_SHAPER_CONTROL[mpcc_inst], + MPCC_MCM_SHAPER_MODE_CURRENT, &s->shaper_lut_mode); +} + static const struct mpc_funcs dcn401_mpc_funcs = { - .read_mpcc_state = mpc1_read_mpcc_state, + .read_mpcc_state = mpc401_read_mpcc_state, .insert_plane = mpc1_insert_plane, .remove_mpcc = mpc1_remove_mpcc, .mpc_init = mpc32_mpc_init, -- 2.34.1
