This series adds CWSR and trap handler support for AMDGPU user queues.
The series introduces the core CWSR infrastructure, including save-area
sizing and validation, and integrates the first-level CWSR trap handler
with the device and user queue lifecycle.
For compute user queues, userspace can provide the context save-area
address and size through the MQD input. The kernel validates the
save-area parameters and the associated GPU virtual address before
using them for queue initialization.
The series also adds userspace interfaces to query the required CWSR
save-area sizes and configure a second-level trap handler. An additional
interface allows controlling the debugger trap flag in the TMA region.
As the resulting infrastructure manages more than CWSR alone, the final
patch renames the generic amdgpu_cwsr infrastructure to amdgpu_trap.
CWSR-specific terminology is retained for functionality and data that
are specifically related to compute wave save/restore.
This series is based on the CWSR and trap-handler work from the
amd-unified-interface topic branch. The prerequisite changes were
cherry-picked and rebased onto amd-staging-drm-next, with closely
related commits squashed into logical review units for submission.
The following commits from amd-unified-interface were used as the basis
for this series:
4cd417bfec49 drm/amdgpu: Add helper function to get xcc count
c50a45b2e98d drm/amdgpu: Add cwsr functions
df9097c600d2 drm/amdgpu: Fill cwsr save area details
b3d79401d5eb drm/amdgpu: Add user save area params validation
09673227ef61 drm/amdgpu: Add cwsr to device init/fini sequence
6748338e7d6e drm/amdgpu: Add first level cwsr handler to userq
7ca9abf4ac38 drm/amdgpu: Add user save area params to mqd input
2b419a703c20 drm/amdgpu: Add ioctl to get cwsr details
310b37612d61 drm/amdgpu: Add ioctl support for cwsr params
633f9544e6d8 drm/amdgpu: Add ioctl to set level2 handler
7289d8136917 drm/amdgpu: Add interface to set debug trap flag
71c944500a84 drm/amdgpu: Rename amdgpu_cwsr to amdgpu_trap
a0fe30c73b88 drm/amdgpu: Fix recursive ww_mutex lock in
amdgpu_trap_alloc
The recursive ww_mutex locking correction from a0fe30c73b88 has been
folded into the patch that introduces the core CWSR allocation path.
The original allocation path acquired the VM reservation through
drm_exec and subsequently created the per-VM TMA BO through a path that
could attempt to acquire a reservation_ww_class_mutex again. The
submitted series instead creates the TMA BO using the VM root BO
reservation object from the beginning, avoiding the recursive
reservation locking problem.
This prevents the series from containing an intermediate commit with
the known recursive locking issue.
The following user queue validation fix has also been folded into the
patch that introduces the user save-area parameters for MQD input:
drm/amdgpu/userq: reserve the VM root BO around CWSR param validation
https://patchwork.freedesktop.org/patch/755116/?series=174525&rev=2
The CWSR/trap parameter validation eventually walks the VM mapping tree
through the user queue VA validation path. The submitted version holds
the VM root BO reservation around this validation, consistent with the
locking requirements of the VM mapping state.
Folding this correction into the introducing patch similarly avoids an
intermediate state where compute queue creation can reach the VA
validation path without the required VM reservation held.
After squashing and reorganizing the prerequisite work, the series is
structured as follows:
1. drm/amdgpu: Add helper function to get xcc count
2. drm/amdgpu: Add CWSR functions and save area handling
3. drm/amdgpu: Enable CWSR for user queues
4. drm/amdgpu: Add user save area params to mqd input
5. drm/amdgpu: Add ioctl to get cwsr details
6. drm/amdgpu: Add ioctl support for cwsr params
7. drm/amdgpu: Add ioctl to set level2 handler
8. drm/amdgpu: Add interface to set debug trap flag
9. drm/amdgpu: Rename amdgpu_cwsr to amdgpu_trap
The two locking corrections are therefore present in the patches that
introduce the corresponding functionality rather than being submitted
as follow-up fixes later in the series.
Thanks,
Srini
Lijo Lazar (8):
drm/amdgpu: Add helper function to get xcc count
drm/amdgpu: Add CWSR functions and save area handling
drm/amdgpu: Enable CWSR for user queues
drm/amdgpu: Add user save area params to mqd input
drm/amdgpu: Add ioctl to get cwsr details
drm/amdgpu: Add ioctl support for cwsr params
drm/amdgpu: Add ioctl to set level2 handler
drm/amdgpu: Add interface to set debug trap flag
Srinivasan Shanmugam (1):
drm/amdgpu: Rename amdgpu_cwsr to amdgpu_trap
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 21 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 31 +
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 8 +
drivers/gpu/drm/amd/amdgpu/amdgpu_trap.c | 655 +++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_trap.h | 101 ++++
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 24 +
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 7 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 13 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h | 22 +
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 14 +
drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 107 +++-
include/uapi/drm/amdgpu_drm.h | 50 ++
15 files changed, 1034 insertions(+), 34 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_trap.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_trap.h
--
2.34.1
