[PATCH 1/4] drm/amd/pm: Update smu_v15_0_8 PMFW headers

[Asad Kamal]

Update smu_v15_0_8 PMFW headers to include NPM metrics

Signed-off-by: Asad Kamal <asad.ka...@amd.com>
Reviewed-by: Lijo Lazar <lijo.la...@amd.com>
---
 .../drm/amd/pm/swsmu/inc/pmfw_if/smu_v15_0_8_pmfw.h  | 12 +++++++++---
 .../drm/amd/pm/swsmu/inc/pmfw_if/smu_v15_0_8_ppsmc.h |  4 +++-
 drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c |  2 +-
 3 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v15_0_8_pmfw.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v15_0_8_pmfw.h
index a3401c4cc20b..61d76ebfdbd4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v15_0_8_pmfw.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v15_0_8_pmfw.h
@@ -328,7 +328,7 @@ typedef struct __attribute__((packed, aligned(4))) {
   uint64_t GfxclkLowUtilizationAcc[8];
 } MetricsTable_t;
 
-#define SMU_SYSTEM_METRICS_TABLE_VERSION 0x1
+#define SMU_SYSTEM_METRICS_TABLE_VERSION 0x2
 
 #pragma pack(push, 4)
 typedef struct {
@@ -343,9 +343,13 @@ typedef struct {
   //NPM: NODE POWER MANAGEMENT
   uint32_t NodePowerLimit;
   uint32_t NodePower;
-  uint32_t GlobalPPTResidencyAcc;
+  uint32_t NPMResidencyAcc;
 
   uint16_t SystemPower[SYSTEM_POWER_MAX_ENTRIES];           // UBB Current 
Power and Power Threshold
+
+  // NPM flags
+  uint32_t NpmSupported;
+  uint32_t NpmEnabled;
 } SystemMetricsTable_t;
 #pragma pack(pop)
 
@@ -368,7 +372,7 @@ typedef struct __attribute__((aligned(4))) {
   uint8_t  FruId[PRODUCT_FRU_ID_LEN];
 } FRUProductInfo_t;
 
-#define SMU_STATIC_METRICS_TABLE_VERSION 0x1
+#define SMU_STATIC_METRICS_TABLE_VERSION 0x2
 
 #pragma pack(push, 4)
 typedef struct {
@@ -421,6 +425,8 @@ typedef struct {
   uint32_t PPT1Max;
   uint32_t PPT1Min;
   uint32_t PPT1Default;
+
+  uint32_t MaxNodePowerLimit;
 } StaticMetricsTable_t;
 #pragma pack(pop)
 
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v15_0_8_ppsmc.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v15_0_8_ppsmc.h
index 7ffb445f4c0c..bf73d10c0ce7 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v15_0_8_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v15_0_8_ppsmc.h
@@ -83,7 +83,9 @@
 #define PPSMC_MSG_SetSoftMaxGl2clk                     0x32
 #define PPSMC_MSG_SetSoftMinFclk                       0x33
 #define PPSMC_MSG_SetSoftMaxFclk                       0x34
-#define PPSMC_Message_Count                         0x35
+/* NPM limit setter; NPM reads are served from the SystemMetricsTable. */
+#define PPSMC_MSG_SetNpmLimit                       0x40
+#define PPSMC_Message_Count                         0x41
 
 /* PSMC Reset Types for driver msg argument */
 #define PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET        0x1
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
index 1b5a31163f3c..a013ae2a877e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
@@ -622,7 +622,7 @@ static int smu_v15_0_8_get_npm_data(struct smu_context *smu,
                *value = !!SMUQ10_ROUND(metrics->NodePower);
                break;
        case AMDGPU_PP_SENSOR_GPPTRESIDENCY:
-               *value = SMUQ10_ROUND(metrics->GlobalPPTResidencyAcc);
+               *value = SMUQ10_ROUND(metrics->NPMResidencyAcc);
                break;
        default:
                return -EINVAL;
-- 
2.46.0