Mesa will use it to get the slice offset in bitstream from feedback, which makes it possible to filter out SPS/PPS headers that VCE 1 and 2 FW always forces on IDR frames.
Bump driver version so that Mesa can use it. Signed-off-by: David Rosca <[email protected]> --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 9c5e93cd3ee6..bb8e3e7b953c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -128,9 +128,10 @@ * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size * - 3.64.0 - Userq IP support query * - 3.65.0 - Add userq syncobj timeline signaling support + * - 3.66.0 - VCE SEI command and fixes */ #define KMS_DRIVER_MAJOR 3 -#define KMS_DRIVER_MINOR 65 +#define KMS_DRIVER_MINOR 66 #define KMS_DRIVER_PATCHLEVEL 0 /* diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 2e1a48dafd21..c18741d16ad8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -925,6 +925,7 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, case 0x04000007: /* motion estimation */ case 0x04000008: /* rdo */ case 0x04000009: /* vui */ + case 0x0400000d: /* sei */ case 0x05000002: /* auxiliary buffer */ case 0x05000009: /* clock table */ break; -- 2.43.0
