On Fri, Oct 9, 2026 at 12:26 PM Tom St Denis <[email protected]> wrote: > > This adds the regCP_ME1_INT_STAT_DEBUG and regCP_ME2_INT_STAT_DEBUG registers > that > were missing from the GC 11.0.0 headers but found in GC 11.0.3 > > Signed-off-by: Tom St Denis <[email protected]>
Acked-by: Alex Deucher <[email protected]> > --- > .../include/asic_reg/gc/gc_11_0_0_offset.h | 4 ++ > .../include/asic_reg/gc/gc_11_0_0_sh_mask.h | 54 +++++++++++++++++++ > 2 files changed, 58 insertions(+) > > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h > b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h > index a3bcdf632066..3dddaec23bcf 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h > @@ -4261,6 +4261,10 @@ > #define regCP_ME2_PIPE2_INT_STATUS_BASE_IDX > 0 > #define regCP_ME2_PIPE3_INT_STATUS > 0x1e34 > #define regCP_ME2_PIPE3_INT_STATUS_BASE_IDX > 0 > +#define regCP_ME1_INT_STAT_DEBUG > 0x1e35 > +#define regCP_ME1_INT_STAT_DEBUG_BASE_IDX > 0 > +#define regCP_ME2_INT_STAT_DEBUG > 0x1e36 > +#define regCP_ME2_INT_STAT_DEBUG_BASE_IDX > 0 > #define regCP_GFX_QUEUE_INDEX > 0x1e37 > #define regCP_GFX_QUEUE_INDEX_BASE_IDX > 0 > #define regCC_GC_EDC_CONFIG > 0x1e38 > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h > b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h > index 3088a4a13cb5..1b64f157467d 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h > @@ -16187,6 +16187,60 @@ > #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK > 0x00800000L > #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT > 0x17 > #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK > 0x00800000L > +//CP_ME1_INT_STAT_DEBUG > +#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT > 0xc > +#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT > 0xd > +#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT > 0xe > +#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT > 0xf > +#define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT > 0x10 > +#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT > 0x11 > +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT > 0x17 > +#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT > 0x18 > +#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT > 0x1a > +#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT > 0x1b > +#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT > 0x1d > +#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT > 0x1e > +#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT > 0x1f > +#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK > 0x00001000L > +#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK > 0x00002000L > +#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK > 0x00004000L > +#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK > 0x00008000L > +#define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK > 0x00010000L > +#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK > 0x00020000L > +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK > 0x00800000L > +#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK > 0x01000000L > +#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK > 0x04000000L > +#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK > 0x08000000L > +#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK > 0x20000000L > +#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK > 0x40000000L > +#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK > 0x80000000L > +//CP_ME2_INT_STAT_DEBUG > +#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT > 0xc > +#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT > 0xd > +#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT > 0xe > +#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT > 0xf > +#define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT > 0x10 > +#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT > 0x11 > +#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT > 0x17 > +#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT > 0x18 > +#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT > 0x1a > +#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT > 0x1b > +#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT > 0x1d > +#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT > 0x1e > +#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT > 0x1f > +#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK > 0x00001000L > +#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK > 0x00002000L > +#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK > 0x00004000L > +#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK > 0x00008000L > +#define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK > 0x00010000L > +#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK > 0x00020000L > +#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK > 0x00800000L > +#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK > 0x01000000L > +#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK > 0x04000000L > +#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK > 0x08000000L > +#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK > 0x20000000L > +#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK > 0x40000000L > +#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK > 0x80000000L > //CP_GFX_QUEUE_INDEX > #define CP_GFX_QUEUE_INDEX__QUEUE_ACCESS__SHIFT > 0x0 > #define CP_GFX_QUEUE_INDEX__PIPE_ID__SHIFT > 0x4 > -- > 2.53.0 >
