the register c2pmsg_127 design only applies to dGPU not
APU platform, so hard code ras block feature mask on APU
platform.

Signed-off-by: Stanley.Yang <[email protected]>
---
 drivers/gpu/drm/amd/ras/core/ras_psp_v13_0.c | 14 ++++++++++++--
 drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h    |  6 ++++++
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/ras/core/ras_psp_v13_0.c 
b/drivers/gpu/drm/amd/ras/core/ras_psp_v13_0.c
index 49ba57f58878c..fe971cf19e493 100644
--- a/drivers/gpu/drm/amd/ras/core/ras_psp_v13_0.c
+++ b/drivers/gpu/drm/amd/ras/core/ras_psp_v13_0.c
@@ -80,13 +80,23 @@ static int ras_psp_v13_0_get_ras_block_maps(struct 
ras_core_context *ras_core,
 static int ras_psp_v13_0_get_ras_hw_caps(struct ras_core_context *ras_core,
                                struct ras_hw_caps *ras_cap)
 {
-       uint32_t ras_hw_cap, bit;
+       uint32_t ras_hw_cap = 0, bit;
        uint32_t i;
 
        if (!ras_cap)
                return -EINVAL;
 
-       ras_hw_cap = RAS_DEV_RREG32_SOC15(ras_core->dev, MP0, 0, 
regMP0_SMN_C2PMSG_127);
+       /*
+        * driver only manages a few IP block RAS fearure
+        * when GPU is connected CPU through XGMI
+        */
+       if (RAS_DEV_GET_DEVICE_FLAGS(ras_core->dev) & AMD_IS_APU) {
+               ras_hw_cap |= (1 << AMDGPU_RAS_BLOCK__GFX |
+                                          1 << AMDGPU_RAS_BLOCK__SDMA |
+                                          1 << AMDGPU_RAS_BLOCK__MMHUB);
+       } else {
+               ras_hw_cap = RAS_DEV_RREG32_SOC15(ras_core->dev, MP0, 0, 
regMP0_SMN_C2PMSG_127);
+       }
 
        ras_cap->poison_supported = true;
        ras_cap->flex_mca_enabled = false;
diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h 
b/drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h
index de3da5571ef82..fada8b1b41453 100644
--- a/drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h
+++ b/drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h
@@ -107,6 +107,12 @@
                adev->ip_map.logical_to_dev_mask(adev, ip##_HWIP, mask) : 
mask); \
 })
 
+#define RAS_DEV_GET_DEVICE_FLAGS(dev) \
+({ \
+       struct amdgpu_device *adev = (struct amdgpu_device *)dev; \
+       adev->flags; \
+})
+
 static inline void *ras_radix_tree_delete_iter(struct radix_tree_root *root, 
void *iter)
 {
        return radix_tree_delete(root, ((struct radix_tree_iter *)iter)->index);
-- 
2.43.0

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