AMD General

Reviewed-by: Hawking Zhang <[email protected]>

Regards,
Hawking
-----Original Message-----
From: Yang, Stanley <[email protected]>
Sent: Wednesday, October 14, 2026 8:54 PM
To: [email protected]
Cc: Zhang, Hawking <[email protected]>; Zhou1, Tao <[email protected]>; 
Chai, Thomas <[email protected]>; Li, Candice <[email protected]>; Liu, 
Xiang(Dean) <[email protected]>; Sun, Ce(Overlord) <[email protected]>; Xie, 
Patrick <[email protected]>; Yang, Stanley <[email protected]>
Subject: [PATCH Review v2 1/1] drm/amd/ras: Fix APU platform ras block feature 
mask

the register c2pmsg_127 design only applies to dGPU not APU platform, so hard 
code ras block feature mask on APU platform.

Changed from v1:
        replace AMD_IS_APU with is_app_apu for judgment

Signed-off-by: Stanley.Yang <[email protected]>
---
 drivers/gpu/drm/amd/ras/core/ras_psp_v13_0.c | 14 ++++++++++++--
 drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h    |  6 ++++++
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/ras/core/ras_psp_v13_0.c 
b/drivers/gpu/drm/amd/ras/core/ras_psp_v13_0.c
index 49ba57f58878..bdd3da2c66f3 100644
--- a/drivers/gpu/drm/amd/ras/core/ras_psp_v13_0.c
+++ b/drivers/gpu/drm/amd/ras/core/ras_psp_v13_0.c
@@ -80,13 +80,23 @@ static int ras_psp_v13_0_get_ras_block_maps(struct 
ras_core_context *ras_core,  static int ras_psp_v13_0_get_ras_hw_caps(struct 
ras_core_context *ras_core,
                                struct ras_hw_caps *ras_cap)
 {
-       uint32_t ras_hw_cap, bit;
+       uint32_t ras_hw_cap = 0, bit;
        uint32_t i;

        if (!ras_cap)
                return -EINVAL;

-       ras_hw_cap = RAS_DEV_RREG32_SOC15(ras_core->dev, MP0, 0, 
regMP0_SMN_C2PMSG_127);
+       /*
+        * driver only manages a few IP block RAS fearure
+        * when GPU is connected CPU through XGMI
+        */
+       if (RAS_DEV_IS_APP_APU(ras_core->dev)) {
+               ras_hw_cap |= (1 << AMDGPU_RAS_BLOCK__GFX |
+                                          1 << AMDGPU_RAS_BLOCK__SDMA |
+                                          1 << AMDGPU_RAS_BLOCK__MMHUB);
+       } else {
+               ras_hw_cap = RAS_DEV_RREG32_SOC15(ras_core->dev, MP0, 0, 
regMP0_SMN_C2PMSG_127);
+       }

        ras_cap->poison_supported = true;
        ras_cap->flex_mca_enabled = false;
diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h 
b/drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h
index 1c5e02de7fca..00ff12ccb01a 100644
--- a/drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h
+++ b/drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h
@@ -106,6 +106,12 @@
        amdgpu_ip_map_logical_to_dev_mask(&adev->ip_map, ip##_HWIP, mask); \
 })

+#define RAS_DEV_IS_APP_APU(dev) \
+({ \
+       struct amdgpu_device *adev = (struct amdgpu_device *)dev; \
+       adev->gmc.is_app_apu; \
+})
+
 static inline void *ras_radix_tree_delete_iter(struct radix_tree_root *root, 
void *iter)  {
        return radix_tree_delete(root, ((struct radix_tree_iter *)iter)->index);
--
2.43.0

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