MI300/MI350 have a different register layout, and cannot reuse the same definitions from MI2. The shader cleaner can be reused, but not the initialization steps.
Also change the dim_x to ensure that we cover all wave slots per SIMD. Signed-off-by: Kent Russell <[email protected]> --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c | 37 +++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c index dc46133ed506..7018efbc5e02 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c @@ -23,6 +23,7 @@ #include "amdgpu.h" #include "soc15.h" #include "soc15d.h" +#include "soc15_common.h" #include "gc/gc_9_4_2_offset.h" #include "gc/gc_9_4_2_sh_mask.h" @@ -365,6 +366,20 @@ const struct soc15_reg_entry fault_cleaner_init_regs_aldebaran[] = { { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, }; +static const struct soc15_reg_entry fault_cleaner_init_regs_aqua_vanjaram[] = { + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_RESOURCE_LIMITS), 0x000000000 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_X), 0x40 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Y), 1 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Z), 1 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC1), 0x00af0000 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC2), 0x000000c0 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC3), 0x00000000 }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, + { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, +}; + static int gfx_v9_4_2_run_shader(struct amdgpu_device *adev, struct amdgpu_ring *ring, const u32 *shader_ptr, u32 shader_size, @@ -723,6 +738,8 @@ static int gfx_v9_clean_shaders(struct amdgpu_device *adev) struct amdgpu_ib wb_ib; struct amdgpu_ring *ring; struct dma_fence *fence = NULL; + const struct soc15_reg_entry *init_regs; + u32 init_regs_size; u32 pattern = 0xa; int xcc_id; @@ -731,6 +748,20 @@ static int gfx_v9_clean_shaders(struct amdgpu_device *adev) return 0; } + /* gfx943+ has different register layout compared to gfx942.*/ + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { + case IP_VERSION(9, 4, 3): + case IP_VERSION(9, 4, 4): + case IP_VERSION(9, 5, 0): + init_regs = fault_cleaner_init_regs_aqua_vanjaram; + init_regs_size = ARRAY_SIZE(fault_cleaner_init_regs_aqua_vanjaram); + break; + default: + init_regs = fault_cleaner_init_regs_aldebaran; + init_regs_size = ARRAY_SIZE(fault_cleaner_init_regs_aldebaran); + break; + } + for_each_inst(xcc_id, adev->gfx.xcc_mask) { ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings]; @@ -752,9 +783,9 @@ static int gfx_v9_clean_shaders(struct amdgpu_device *adev) ring, fault_cleaner_compute_shader_aldebaran, sizeof(fault_cleaner_compute_shader_aldebaran), - fault_cleaner_init_regs_aldebaran, - ARRAY_SIZE(fault_cleaner_init_regs_aldebaran), - adev->gfx.cu_info.number * 32, + init_regs, + init_regs_size, + adev->gfx.cu_info.number * SIMD_ID_MAX * WAVE_ID_MAX, wb_ib.gpu_addr, pattern, &fence); if (r) { -- 2.43.0
