This patch series reworks the amdgpu open/close, vm, cs, and validation
functionality to allow for access of the GPU's CPU sided bookkeeping
data without waking up the GPU from idle.
The overhaul will allow a few tools to function without waking up the
GPU, which can improve power efficiency within relevant domains, and can
hopefully be expanded on later to adapt for useful utilities.
v2:
- Force a vm->generation mismatch by adding 1 to the result of
amdgpu_vm_generation.
- Separate validation logic from patch "drm/amdgpu: defer GPU resume from
open/close to first use" into a new patch.
- Change validation logic to not depend on flags to operate. Instead
relying on a vm->generation mismatch.
- Clear vm pts in the kernel.evicted loop instead.
- Remove the root_cleared flag.
- Let the vm domain be initialized to VRAM in amdgpu_vm_pt_create if the
vm->root.bo is not null.
- Clear the root page table on vm_init if pm_ref was true.
v3:
- Merged: commit fbbcdad4c7c8 ("drm/amdgpu: clear vm pts upon a
vm->generation mismatch")
- Remove pm_runtime_get_sync() and pm_runtime_put_autosuspend() from
open/postclose kms.
- Remove the powered_init flag and parameter to vm_init.
- Remove amdgpu_vm_generation() result + 1 patch to instead depend on
setting vm->generation to ~0ULL to force the mismatch.
- Initialize the root PD's domain to 0 (system memory) instead of GTT.
- Add validation handling in accordance with amdgpu_ualink.c vm
initialization.
Concerns:
In the first patch, amdgpu_vm_init() reserved a fence slot for
amdgpu_vm_pt_clear() prior to this patch set:
r = dma_resv_reserve_fences(root_bo->tbo.base.resv, 1);
if (r)
goto error_free_root;
- r = amdgpu_vm_pt_clear(adev, vm, root, false);
Due to my limited knowledge on how fences function and when they are
required, I wasn't sure whether I had to replicate this in ualink and
possibly other locations that require amdgpu_vm_validate(). Such as in
amdgpu_amdkfd_gpuvm.c. Since amdgpu_vm_pt_clear is now deferred to
validate.
As a result I left it untouched within those domains and used
amdgpu_ualink_reserve_npa_vm_and_bos() instead of amdgpu_bo_reserve()
for ualink, since the former is native to ualink and reserves both the
bo and fence slots.
This can be easily changed into amdgpu_bo_reserve() in v4 of the patch
if required.
In the second patch, amdgpu_driver_postclose_kms calls functions
amdgpu_uvd_free_handles and amdgpu_vce_free_handles. Both of which
require hardware access. I attempted to test this with a Radeon VII
card, which to my knowledge does utilize these multimedia
specifications. However, I was unable to get the gpu to enter BACO/BOCO
mode and wasn't fully able to test the path.
I'm not sure if it was an exception to my card or BACO/BOCO isn't
supported on those older GFX IPs.
Shahyan Soltani (2):
drm/amdgpu: defer amdgpu_vm_pt_clear() to validation
drm/amdgpu: remove pm_runtime from open/close kms paths
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 18 +++----------
drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c | 31 ++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 +----
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 13 +++++++--
5 files changed, 47 insertions(+), 22 deletions(-)
--
2.56.0
