gfx_v8_0_constants_init() programs the SH_MEM registers of VMID 0 and the kernel queue VMIDs, and gfx_v8_0_init_compute_vmid() those of the user queue VMIDs, each walking its own VMID mask.
Program them in one place, walking the kernel queue and the user queue VMIDs together and giving each the configuration of its users: VMID 0 uncached with null bases, the kernel queue VMIDs non-coherent with the shared aperture, and the user queue VMIDs the HSA64 address mode, cache coherency, ATC for the private aperture and the application apertures; APE1 stays disabled for all of them. The GDS, GWS and OA clearing of the user queue VMIDs in gfx_v8_0_init_compute_vmid() goes away, gfx_v8_0_init_gds_vmid() clears them for all VMIDs but 0 right after. No functional change. Suggested-by: Alex Deucher <[email protected]> Signed-off-by: Jesse Zhang <[email protected]> --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 96 ++++++++++++--------------- 1 file changed, 41 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 7e2f9c13dec3..e634d9fbd4b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -3644,54 +3644,68 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev) #define DEFAULT_SH_MEM_BASES (0x6000) /** - * gfx_v8_0_init_compute_vmid - gart enable + * gfx_v8_0_init_sh_mem - initialize the sh_mem registers of all VMIDs * * @adev: amdgpu_device pointer * - * Initialize compute vmid sh_mem registers - * + * Program the sh_mem registers of VMID 0, the kernel queue VMIDs, including + * the SPM VMID, and the user queue VMIDs in one place, each with the + * configuration of its users. */ -static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev) +static void gfx_v8_0_init_sh_mem(struct amdgpu_device *adev) { + unsigned long uq_mask = adev->vm_manager.vmid_uq_mask_gfxhub; + unsigned long mask = amdgpu_vmid_kq_mask(adev, AMDGPU_GFXHUB(0)) | uq_mask; + u32 vmid0_config, kq_config, uq_config, uq_bases; int i; - uint32_t sh_mem_config; - uint32_t sh_mem_bases; + + vmid0_config = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC); + vmid0_config = REG_SET_FIELD(vmid0_config, SH_MEM_CONFIG, APE1_MTYPE, + MTYPE_UC); + vmid0_config = REG_SET_FIELD(vmid0_config, SH_MEM_CONFIG, ALIGNMENT_MODE, + SH_MEM_ALIGNMENT_MODE_UNALIGNED); + + kq_config = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC); + kq_config = REG_SET_FIELD(kq_config, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC); + kq_config = REG_SET_FIELD(kq_config, SH_MEM_CONFIG, ALIGNMENT_MODE, + SH_MEM_ALIGNMENT_MODE_UNALIGNED); /* - * Configure apertures: + * Configure apertures of the user queue VMIDs: * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) */ - sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); + uq_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); - sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 << - SH_MEM_CONFIG__ADDRESS_MODE__SHIFT | - SH_MEM_ALIGNMENT_MODE_UNALIGNED << - SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT | - MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT | - SH_MEM_CONFIG__PRIVATE_ATC_MASK; + uq_config = SH_MEM_ADDRESS_MODE_HSA64 << + SH_MEM_CONFIG__ADDRESS_MODE__SHIFT | + SH_MEM_ALIGNMENT_MODE_UNALIGNED << + SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT | + MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT | + SH_MEM_CONFIG__PRIVATE_ATC_MASK; mutex_lock(&adev->srbm_mutex); - for_each_uq_gfx_vmid(i, adev) { + for_each_set_bit(i, &mask, AMDGPU_NUM_VMID) { vi_srbm_select(adev, 0, 0, 0, i); /* CP and shaders */ - WREG32(mmSH_MEM_CONFIG, sh_mem_config); + if (uq_mask & BIT(i)) { + WREG32(mmSH_MEM_CONFIG, uq_config); + WREG32(mmSH_MEM_BASES, uq_bases); + } else if (i) { + WREG32(mmSH_MEM_CONFIG, kq_config); + WREG32(mmSH_MEM_BASES, + adev->gmc.shared_aperture_start >> 48); + } else { + WREG32(mmSH_MEM_CONFIG, vmid0_config); + WREG32(mmSH_MEM_BASES, 0); + } + WREG32(mmSH_MEM_APE1_BASE, 1); WREG32(mmSH_MEM_APE1_LIMIT, 0); - WREG32(mmSH_MEM_BASES, sh_mem_bases); } vi_srbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); - - /* Initialize all compute VMIDs to have no GDS, GWS, or OA - access. These should be enabled by FW for target VMIDs. */ - for_each_uq_gfx_vmid(i, adev) { - WREG32(amdgpu_gds_reg_offset[i].mem_base, 0); - WREG32(amdgpu_gds_reg_offset[i].mem_size, 0); - WREG32(amdgpu_gds_reg_offset[i].gws, 0); - WREG32(amdgpu_gds_reg_offset[i].oa, 0); - } } static void gfx_v8_0_init_gds_vmid(struct amdgpu_device *adev) @@ -3728,7 +3742,6 @@ static void gfx_v8_0_config_init(struct amdgpu_device *adev) static void gfx_v8_0_constants_init(struct amdgpu_device *adev) { u32 tmp, sh_static_mem_cfg; - int i; WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF); WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); @@ -3750,34 +3763,7 @@ static void gfx_v8_0_constants_init(struct amdgpu_device *adev) INDEX_STRIDE, 3); WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg); - mutex_lock(&adev->srbm_mutex); - for_each_vmid_and_zero(i, adev, 0) { - vi_srbm_select(adev, 0, 0, 0, i); - /* CP and shaders */ - if (i == 0) { - tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC); - tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC); - tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, - SH_MEM_ALIGNMENT_MODE_UNALIGNED); - WREG32(mmSH_MEM_CONFIG, tmp); - WREG32(mmSH_MEM_BASES, 0); - } else { - tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC); - tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC); - tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, - SH_MEM_ALIGNMENT_MODE_UNALIGNED); - WREG32(mmSH_MEM_CONFIG, tmp); - tmp = adev->gmc.shared_aperture_start >> 48; - WREG32(mmSH_MEM_BASES, tmp); - } - - WREG32(mmSH_MEM_APE1_BASE, 1); - WREG32(mmSH_MEM_APE1_LIMIT, 0); - } - vi_srbm_select(adev, 0, 0, 0, 0); - mutex_unlock(&adev->srbm_mutex); - - gfx_v8_0_init_compute_vmid(adev); + gfx_v8_0_init_sh_mem(adev); gfx_v8_0_init_gds_vmid(adev); mutex_lock(&adev->grbm_idx_mutex); -- 2.50.1
