On Tue, Nov 3, 2026 at 10:25 AM André Eikmeyer <[email protected]> wrote: > > On Tue, 3 Nov 2026 09:30:34 -0500 > Alex Deucher <[email protected]> wrote: > > > It is the same issue. I don't want two fixes for the same issue. > > Understandable, but it is not. Two devs told you the same > independently. > On another note I reviewed your patch. It only rejects empty or zero > levels. On the 16,1 the pptable levels (736/750 MHz) are non-zero. > Besides other issues in the code, the commit message says the exact > patch wasn't tested, yet v5 extends it to every Apple Navi 1x. > I am sorry but your patch is implausible to me.
I forgot to remove the pptable check. Can you try a simplified version of the patch? I think all you need to do is delay the UCLK DPM enablement until late_init. Something like the attached patch. Alex
From 0cf8c5010875a2cf2574be2bfb690fd85a0da748 Mon Sep 17 00:00:00 2001 From: Atharva Tiwari <[email protected]> Date: Wed, 16 Sep 2026 14:40:14 +0000 Subject: [PATCH] drm/amd/pm: defer UCLK DPM on selected Apple Navi GPUs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Apple Navi GPUs intermittently time out during SMU initialization when EnableAllSmuFeatures includes UCLK DPM. Leave UCLK out of that early request and enable it from Navi post-init, after display hardware init and before the UMC workaround and UMD clock setup. Read back the enabled features before rebuilding the memory clock table and sustainable clock limits. Also check the PPT memory states used by display initialization before late enablement. Keep memory-voltage DPM and respect the user's memory-DPM setting and the secure Navi 10 exclusion. This builds on Atharva Tiwari's submitted 0219 delayed-UCLK patch and Guna's diagnosis. Ed Schofield moved the enable point into the Navi callback, added state validation. Independent tests of the related T2 implementation support improved boot reliability on 0219 and 021a; those are not tests of this exact AMD patch. Link: https://lore.kernel.org/amd-gfx/[email protected]/ Link: https://github.com/t2linux/linux-t2-patches/pull/61#issuecomment-5637976466 Link: https://github.com/t2linux/linux-t2-patches/pull/61#issuecomment-5645652752 Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/6005 Assisted-by: Codex:GPT-6 Cc: André Eikmeyer <[email protected]> Signed-off-by: Atharva Tiwari <[email protected]> Co-developed-by: Ed Schofield <[email protected]> Signed-off-by: Ed Schofield <[email protected]> Signed-off-by: Alex Deucher <[email protected]> --- .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index 2d05088619f6d..672d740e72883 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -60,6 +60,25 @@ static int navi10_init_ppt_limits(struct smu_context *smu); +static bool is_asic_secure(struct smu_context *smu); + +static bool navi10_apple_needs_late_uclk(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + struct pci_dev *pdev = adev->pdev; + + if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) + return false; + + /* Preserve the existing secure Navi 10 memory-DPM exclusion. */ + if (is_asic_secure(smu) && + amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0) && + adev->rev_id == 0) + return false; + + return pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE; +} + static const struct smu_feature_bits navi10_dpm_features = { .bits = { SMU_FEATURE_BIT_INIT(FEATURE_DPM_PREFETCHER_BIT), @@ -356,6 +375,11 @@ navi10_init_allowed_features(struct smu_context *smu) smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_MVDD_SCALING_BIT); } + /* Defer UCLK on the selected Apple boards until IP late init. */ + if (navi10_apple_needs_late_uclk(smu)) + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, + FEATURE_DPM_UCLK_BIT); + if (is_asic_secure(smu) && (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) && (adev->rev_id == 0)) @@ -3219,6 +3243,30 @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu) NULL); } +/* IP late init follows display hw_init; refresh clocks before UMC/UMD setup. */ +static int navi10_apple_late_uclk_enable(struct smu_context *smu) +{ + struct smu_feature_bits enabled; + int ret; + + if (!navi10_apple_needs_late_uclk(smu)) + return 0; + + ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT, true); + if (ret) + return ret; + ret = smu_cmn_get_enabled_mask(smu, &enabled); + if (ret) + return ret; + if (!smu_feature_bits_is_set(&enabled, FEATURE_DPM_UCLK_BIT)) + return -EIO; + + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_SUPPORTED, + FEATURE_DPM_UCLK_BIT); + + return 0; +} + static int navi10_post_smu_init(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; @@ -3227,6 +3275,12 @@ static int navi10_post_smu_init(struct smu_context *smu) if (amdgpu_sriov_vf(adev)) return 0; + ret = navi10_apple_late_uclk_enable(smu); + if (ret) { + dev_err(adev->dev, "Failed to enable late UCLK DPM: %d\n", ret); + return ret; + } + ret = navi10_run_umc_cdr_workaround(smu); if (ret) dev_err(adev->dev, "Failed to apply umc cdr workaround!\n"); -- 2.56.0
