AMD General > -----Original Message----- > From: Koenig, Christian <[email protected]> > Sent: Friday, November 6, 2026 4:15 PM > To: Zhang, Jesse(Jie) <[email protected]>; amd- > [email protected] > Cc: Deucher, Alexander <[email protected]>; Lazar, Lijo > <[email protected]>; SHANMUGAM, SRINIVASAN > <[email protected]> > Subject: Re: [PATCH] drm/amdgpu: don't create the CWSR TMA BO as a kernel > BO > > On 11/6/26 08:25, Jesse Zhang wrote: > > amdgpu_cwsr_alloc() creates the TMA BO of every opened render node > > with the resv of the VM root PD and as ttm_bo_type_kernel. The VM puts > > kernel BOs which share its resv on its page table lists, so the TMA BO > > is treated as a page table: after a VRAM losing reset its bo_va moves > > to the page tables needing an update, and amdgpu_vm_update_pdes() > > tries to write its PDE. It has no parent page directory, so that > > fails, and fails again on every following submission of the file. > > > > On navi31, submitting on a render node, then amdgpu_gpu_recover and > > submitting again, also with a new context: > > > > amdgpu 0000:03:00.0: VRAM is lost due to GPU reset! > > amdgpu 0000:03:00.0: GPU reset(1) succeeded! > > WARNING: amdgpu_vm_pt.c:664 at > amdgpu_vm_pde_update+0x329/0x5d0 > > [amdgpu], CPU#3: vmreinit/2728 > > > > and every command submission fails with -EINVAL from then on. > > > > Create the TMA BO as a device BO, a per VM BO like the other ones. > > With that the submissions after the reset complete. > > > > Fixes: 8a93aae9896b ("drm/amdgpu: Add CWSR infrastructure for user > > queues") > > Signed-off-by: Jesse Zhang <[email protected]> > > Clear NAK, that allows to mmap the CWSR BO from userspace and that in turn > is seen as highly problematic. > > IIRC Sunil already stumbled over this issue as well and we agreed to not check > for ttm_bo_type_kernel any more. > > Could be that Sunil and I didn't fix all problems with this, maybe take a > look at > the history of amdgpu_vm.c.
Agreed, thanks. The remaining type check was in amdgpu_vm_bo_lock_lists(), which still put every always valid ttm_bo_type_kernel BO on the PD/PT lists (the TMA BO included). v2 keeps the TMA BO a kernel BO and lets the creator of the vm_bo tell whether it is a PD/PT (new amdgpu_vm_bo_base::page_table), similar to what Sunil did for amdgpu_vm_bo_needs_update(). Thanks Jesse > > Regards, > Christian. > > > --- > > drivers/gpu/drm/amd/amdgpu/amdgpu_cwsr.c | 6 +++++- > > 1 file changed, 5 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cwsr.c > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_cwsr.c > > index daca0a1ac990..52ae77a08ca0 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cwsr.c > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cwsr.c > > @@ -433,7 +433,11 @@ int amdgpu_cwsr_alloc(struct amdgpu_device > *adev, struct amdgpu_vm *vm, > > bp.domain = AMDGPU_GEM_DOMAIN_GTT; > > bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC | > > AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; > > - bp.type = ttm_bo_type_kernel; > > + /* > > + * Not ttm_bo_type_kernel: the VM takes kernel BOs sharing its resv > > + * for page tables. > > + */ > > + bp.type = ttm_bo_type_device; > > bp.bo_ptr_size = sizeof(struct amdgpu_bo); > > bp.resv = vm->root.bo->tbo.base.resv; > >
