Cleanup asic_reg/raven1/THM folder. Change-Id: I088cd61f42ee88ccf0c327b139d7a34c0fdadea5 Signed-off-by: Feifei Xu <[email protected]> --- .../drm/amd/include/asic_reg/{raven1/THM => thm}/thm_10_0_default.h | 0 .../drm/amd/include/asic_reg/{raven1/THM => thm}/thm_10_0_offset.h | 0 .../drm/amd/include/asic_reg/{raven1/THM => thm}/thm_10_0_sh_mask.h | 0 drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h | 6 +++--- 4 files changed, 3 insertions(+), 3 deletions(-) rename drivers/gpu/drm/amd/include/asic_reg/{raven1/THM => thm}/thm_10_0_default.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{raven1/THM => thm}/thm_10_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{raven1/THM => thm}/thm_10_0_sh_mask.h (100%)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_default.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_default.h rename to drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_default.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_offset.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_offset.h rename to drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_sh_mask.h similarity index 100% rename from drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_sh_mask.h rename to drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h index 5fb38f6..ae59a3f 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h @@ -33,9 +33,9 @@ #include "asic_reg/nbio/nbio_7_0_offset.h" #include "asic_reg/nbio/nbio_7_0_sh_mask.h" -#include "asic_reg/raven1/THM/thm_10_0_default.h" -#include "asic_reg/raven1/THM/thm_10_0_offset.h" -#include "asic_reg/raven1/THM/thm_10_0_sh_mask.h" +#include "asic_reg/thm/thm_10_0_default.h" +#include "asic_reg/thm/thm_10_0_offset.h" +#include "asic_reg/thm/thm_10_0_sh_mask.h" #define ixDDI_PHY_GEN_STATUS 0x3FCE8 -- 2.7.4 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
