From: Tony Cheng <[email protected]> REG_UPDATE_2 return the reg value it write out through MMIO we need to do a REG_READ to confirm the value is written out
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c index 1984ac2eb740..2d843b2d5f86 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c @@ -42,13 +42,14 @@ void hubp1_set_blank(struct hubp *hubp, bool blank) { struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); uint32_t blank_en = blank ? 1 : 0; - uint32_t reg_val = 0; - reg_val = REG_UPDATE_2(DCHUBP_CNTL, + REG_UPDATE_2(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en, HUBP_TTU_DISABLE, blank_en); if (blank) { + uint32_t reg_val = REG_READ(DCHUBP_CNTL); + if (reg_val) { /* init sequence workaround: in case HUBP is * power gated, this wait would timeout. -- 2.14.1 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
