On Thu, Feb 1, 2018 at 11:52 PM, Rex Zhu <rex....@amd.com> wrote:
> Change-Id: I2d7663e164ff8eeafe0a4fed99e106b1d130a285
> Signed-off-by: Rex Zhu <rex....@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index ba3c7d6..6700839 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -2919,10 +2919,10 @@ static int smu7_apply_state_adjust_rules(struct 
> pp_hwmgr *hwmgr,
>                                     
> PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
>
>
> -       disable_mclk_switching = ((1 < info.display_count) ||
> -                                 disable_mclk_switching_for_frame_lock ||
> +       disable_mclk_switching = ((1 < info.display_count) &&
> +                                 (disable_mclk_switching_for_frame_lock ||
>                                   smu7_vblank_too_short(hwmgr, 
> mode_info.vblank_time_us) ||
> -                                 (mode_info.refresh_rate > 120));
> +                                 (mode_info.refresh_rate > 120)));

I think this will break the logic to handle single display over 120 hz
and the vblank too short cases.  I think you want 1 <= display_count.
It might be better to make the logic more clear.  How about the
attached patch?

Alex

>
>         sclk = smu7_ps->performance_levels[0].engine_clock;
>         mclk = smu7_ps->performance_levels[0].memory_clock;
> --
> 1.9.1
>
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From bc82506320e594b1b46515ff09c080187f3d2656 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deuc...@amd.com>
Date: Fri, 2 Feb 2018 10:19:13 -0500
Subject: [PATCH] drm/amd/pp: fix mclk fixed in high when no display connected
 (v2)

Also clean up the logic to make it clearer how mclk switching
is determined.

v2: Make the logic clearer, fix the single display case.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index c59cb9499e06..bc56e6f2f7a9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2903,11 +2903,18 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
 				    hwmgr->platform_descriptor.platformCaps,
 				    PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
 
-
-	disable_mclk_switching = ((1 < info.display_count) ||
-				  disable_mclk_switching_for_frame_lock ||
-				  smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us) ||
-				  (mode_info.refresh_rate > 120));
+	if (info.display_count == 0)
+		/* no displays, enable mclk switching */
+		disable_mclk_switching = false;
+	else if (info.display_count == 1)
+		/* 1 display, enable mclk switching if possible */
+		disable_mclk_switching =
+			disable_mclk_switching_for_frame_lock ||
+			smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us) ||
+			(mode_info.refresh_rate > 120);
+	else
+		/* >1 display, disable mclk switching */
+		disable_mclk_switching = true;
 
 	sclk = smu7_ps->performance_levels[0].engine_clock;
 	mclk = smu7_ps->performance_levels[0].memory_clock;
-- 
2.13.6

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