Change-Id: I67597a70008a93381e9bbe2439851e50f012d5ff
Signed-off-by: Rex Zhu <rex....@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c   |  3 +-
 drivers/gpu/drm/amd/powerplay/inc/smumgr.h       |  5 ++
 drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c | 60 +++++++++++++++---------
 drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h | 11 +----
 4 files changed, 44 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index 474612f..4bdb28f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -34,7 +34,6 @@
 #include "rv_ppsmc.h"
 #include "rv_hwmgr.h"
 #include "power_state.h"
-#include "rv_smumgr.h"
 #include "pp_soc15.h"
 
 #define RAVEN_MAX_DEEPSLEEP_DIVIDER_ID     5
@@ -347,7 +346,7 @@ static int rv_populate_clock_table(struct pp_hwmgr *hwmgr)
        DpmClocks_t  *table = &(rv_data->clock_table);
        struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
 
-       result = rv_copy_table_from_smc(hwmgr, (uint8_t *)table, CLOCKTABLE);
+       result = smum_smc_table_manager(hwmgr, (uint8_t *)table, 
SMU10_CLOCKTABLE, true);
 
        PP_ASSERT_WITH_CODE((0 == result),
                        "Attempt to copy clock table from smc failed",
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index cbb0166..4764132 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -82,6 +82,11 @@ enum SMU_MAC_DEFINITION {
        SMU_UVD_MCLK_HANDSHAKE_DISABLE,
 };
 
+enum SMU10_TABLE_ID {
+       SMU10_WMTABLE = 0,
+       SMU10_CLOCKTABLE,
+};
+
 extern int smum_get_argument(struct pp_hwmgr *hwmgr);
 
 extern int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
index 7f2866c..d59ad5e 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
@@ -125,7 +125,7 @@ static int rv_send_msg_to_smc_with_parameter(struct 
pp_hwmgr *hwmgr,
        return 0;
 }
 
-int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr,
+static int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr,
                uint8_t *table, int16_t table_id)
 {
        struct rv_smumgr *priv =
@@ -153,7 +153,7 @@ int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr,
        return 0;
 }
 
-int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr,
+static int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr,
                uint8_t *table, int16_t table_id)
 {
        struct rv_smumgr *priv =
@@ -232,12 +232,12 @@ static int rv_smu_fini(struct pp_hwmgr *hwmgr)
        if (priv) {
                rv_smc_disable_sdma(hwmgr);
                rv_smc_disable_vcn(hwmgr);
-               amdgpu_bo_free_kernel(&priv->smu_tables.entry[WMTABLE].handle,
-                                       
&priv->smu_tables.entry[WMTABLE].mc_addr,
-                                       priv->smu_tables.entry[WMTABLE].table);
-               
amdgpu_bo_free_kernel(&priv->smu_tables.entry[CLOCKTABLE].handle,
-                                       
&priv->smu_tables.entry[CLOCKTABLE].mc_addr,
-                                       
priv->smu_tables.entry[CLOCKTABLE].table);
+               
amdgpu_bo_free_kernel(&priv->smu_tables.entry[SMU10_WMTABLE].handle,
+                                       
&priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,
+                                       
priv->smu_tables.entry[SMU10_WMTABLE].table);
+               
amdgpu_bo_free_kernel(&priv->smu_tables.entry[SMU10_CLOCKTABLE].handle,
+                                       
&priv->smu_tables.entry[SMU10_CLOCKTABLE].mc_addr,
+                                       
priv->smu_tables.entry[SMU10_CLOCKTABLE].table);
                kfree(hwmgr->smu_backend);
                hwmgr->smu_backend = NULL;
        }
@@ -289,12 +289,12 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr)
        if (r)
                return -EINVAL;
 
-       priv->smu_tables.entry[WMTABLE].version = 0x01;
-       priv->smu_tables.entry[WMTABLE].size = sizeof(Watermarks_t);
-       priv->smu_tables.entry[WMTABLE].table_id = TABLE_WATERMARKS;
-       priv->smu_tables.entry[WMTABLE].mc_addr = mc_addr;
-       priv->smu_tables.entry[WMTABLE].table = kaddr;
-       priv->smu_tables.entry[WMTABLE].handle = handle;
+       priv->smu_tables.entry[SMU10_WMTABLE].version = 0x01;
+       priv->smu_tables.entry[SMU10_WMTABLE].size = sizeof(Watermarks_t);
+       priv->smu_tables.entry[SMU10_WMTABLE].table_id = TABLE_WATERMARKS;
+       priv->smu_tables.entry[SMU10_WMTABLE].mc_addr = mc_addr;
+       priv->smu_tables.entry[SMU10_WMTABLE].table = kaddr;
+       priv->smu_tables.entry[SMU10_WMTABLE].handle = handle;
 
        /* allocate space for watermarks table */
        r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
@@ -306,22 +306,35 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr)
                        &kaddr);
 
        if (r) {
-               amdgpu_bo_free_kernel(&priv->smu_tables.entry[WMTABLE].handle,
-                                       
&priv->smu_tables.entry[WMTABLE].mc_addr,
-                                       &priv->smu_tables.entry[WMTABLE].table);
+               
amdgpu_bo_free_kernel(&priv->smu_tables.entry[SMU10_WMTABLE].handle,
+                                       
&priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,
+                                       
&priv->smu_tables.entry[SMU10_WMTABLE].table);
                return -EINVAL;
        }
 
-       priv->smu_tables.entry[CLOCKTABLE].version = 0x01;
-       priv->smu_tables.entry[CLOCKTABLE].size = sizeof(DpmClocks_t);
-       priv->smu_tables.entry[CLOCKTABLE].table_id = TABLE_DPMCLOCKS;
-       priv->smu_tables.entry[CLOCKTABLE].mc_addr = mc_addr;
-       priv->smu_tables.entry[CLOCKTABLE].table = kaddr;
-       priv->smu_tables.entry[CLOCKTABLE].handle = handle;
+       priv->smu_tables.entry[SMU10_CLOCKTABLE].version = 0x01;
+       priv->smu_tables.entry[SMU10_CLOCKTABLE].size = sizeof(DpmClocks_t);
+       priv->smu_tables.entry[SMU10_CLOCKTABLE].table_id = TABLE_DPMCLOCKS;
+       priv->smu_tables.entry[SMU10_CLOCKTABLE].mc_addr = mc_addr;
+       priv->smu_tables.entry[SMU10_CLOCKTABLE].table = kaddr;
+       priv->smu_tables.entry[SMU10_CLOCKTABLE].handle = handle;
 
        return 0;
 }
 
+static int rv_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, 
uint16_t table_id, bool rw)
+{
+       int ret;
+
+       if (rw)
+               ret = rv_copy_table_from_smc(hwmgr, table, table_id);
+       else
+               ret = rv_copy_table_to_smc(hwmgr, table, table_id);
+
+       return ret;
+}
+
+
 const struct pp_smumgr_func rv_smu_funcs = {
        .smu_init = &rv_smu_init,
        .smu_fini = &rv_smu_fini,
@@ -332,6 +345,7 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr)
        .download_pptable_settings = NULL,
        .upload_pptable_settings = NULL,
        .get_argument = rv_read_arg_from_smc,
+       .smc_table_manager = rv_smc_table_manager,
 };
 
 
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h 
b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h
index a3bfdee9..7b53798 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h
@@ -27,11 +27,7 @@
 #include "rv_ppsmc.h"
 #include "smu10_driver_if.h"
 
-enum SMU_TABLE_ID {
-       WMTABLE = 0,
-       CLOCKTABLE,
-       MAX_SMU_TABLE,
-};
+#define MAX_SMU_TABLE 2
 
 struct smu_table_entry {
        uint32_t version;
@@ -50,10 +46,5 @@ struct rv_smumgr {
        struct smu_table_array            smu_tables;
 };
 
-int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr,
-               uint8_t *table, int16_t table_id);
-int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr,
-               uint8_t *table, int16_t table_id);
-
 
 #endif
-- 
1.9.1

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