Ups,
you were faster than ever - my 'double post'
''CONFIG_DRM_AMD_DC_DCN1_0=y' mandatory, again'...;-)
Tested-by: Dieter Nützel <die...@nuetzel-hh.de>
Dieter
Fixes: 680acc64120c (drm/amd/display: Set disp clk in a safe way to
avoid
over high dpp clk.)
Signed-off-by: Harry Wentland <harry.wentland at amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index 76fc903515ba..78e6beb6cf26 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -623,6 +623,7 @@ static bool dce_apply_clock_voltage_request(
}
}
if (send_request) {
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
if (clk->ctx->dce_version >= DCN_VERSION_1_0) {
struct dc *core_dc = clk->ctx->dc;
/*use dcfclk request voltage*/
@@ -630,6 +631,7 @@ static bool dce_apply_clock_voltage_request(
clock_voltage_req.clocks_in_khz =
dcn_find_dcfclk_suits_all(core_dc,
&clk->cur_clocks_value);
}
+#endif
dm_pp_apply_clock_for_voltage_request(
clk->ctx, &clock_voltage_req);
}
--
2.14.1
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