On Tue, Apr 03, 2018 at 05:08:02PM +0800, Emily Deng wrote:
> This adds support for writing and reading back in a single
> oneshot packet. This is needed to send a tlb invalidation
> and wait for ack in a single operation.
>
> Signed-off-by: Emily Deng <emily.d...@amd.com>
> Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 9d39fd5..e699b9e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -4137,6 +4137,18 @@ static void gfx_v9_0_ring_emit_reg_wait(struct
> amdgpu_ring *ring, uint32_t reg,
> gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
> }
>
> +static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
> + uint32_t reg0, uint32_t reg1,
> + uint32_t ref, uint32_t mask)
> +{
> + if (amdgpu_sriov_vf(ring->adev) && (ring->adev->asic_type ==
> CHIP_VEGA10)) {
> + int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
> + gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, ref,
> mask, 0x20);
> + } else {
> + amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
> ref, mask);
> + }
> +}
+ Christian, Tom, I think this is the root cause for regression of raven.
Alex, we need write "1" to set eng_sel field on gfx ring with below patch
that based on you previous patch set. I just verified it, the gfx ring
stall is gone.
Thanks,
Ray
8<-----
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ccacc7d22..2fbb6e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4134,7 +4134,9 @@ static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct
amdgpu_ring *ring,
uint32_t reg0, uint32_t reg1,
uint32_t ref, uint32_t mask)
{
- gfx_v9_0_wait_reg_mem(ring, 0, 0, 1, reg0, reg1, ref, mask, 0x20);
+ int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
+
+ gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, ref, mask, 0x20);
}
static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
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