smu firmware do not update response register immediately under
some delay tasks. so we read out the original value.

so clear the register first.

Signed-off-by: Rex Zhu <rex....@amd.com>
---
 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c   | 4 +---
 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 1 +
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
index 2a93f3a..2d4ec8a 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
@@ -208,9 +208,7 @@ static int ci_send_msg_to_smc(struct pp_hwmgr *hwmgr, 
uint16_t msg)
 {
        int ret;
 
-       if (!ci_is_smc_ram_running(hwmgr))
-               return -EINVAL;
-
+       cgs_write_register(hwmgr->device, mmSMC_RESP_0, 0);
        cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
 
        PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index 10a1123..64d33b7 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -176,6 +176,7 @@ int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t 
msg)
        else if (ret != 1)
                pr_info("\n last message was failed ret is %d\n", ret);
 
+       cgs_write_register(hwmgr->device, mmSMC_RESP_0, 0);
        cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
 
        PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
-- 
1.9.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Reply via email to