On Thu, Jul 5, 2018 at 9:59 AM, Rex Zhu <[email protected]> wrote: > The default clock unit in powerplay is 10KHz. > > Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 +- > drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 3 +-- > 2 files changed, 2 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > index 5e771bc119..eb37316 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > @@ -3801,7 +3801,7 @@ static int > vega10_notify_smc_display_config_after_ps_adjustment( > > if (i < dpm_table->count) { > clock_req.clock_type = amd_pp_dcef_clock; > - clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value; > + clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value > * 10; > if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) > { > smum_send_msg_to_smc_with_parameter( > hwmgr, > PPSMC_MSG_SetMinDeepSleepDcefclk, > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c > index 5749287..ed17c56 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c > @@ -1361,7 +1361,6 @@ int vega12_display_clock_voltage_request(struct > pp_hwmgr *hwmgr, > if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { > switch (clk_type) { > case amd_pp_dcef_clock: > - clk_freq = clock_req->clock_freq_in_khz / 100; > clk_select = PPCLK_DCEFCLK; > break; > case amd_pp_disp_clock: > @@ -1410,7 +1409,7 @@ static int > vega12_notify_smc_display_config_after_ps_adjustment( > > if (data->smu_features[GNLD_DPM_DCEFCLK].supported) { > clock_req.clock_type = amd_pp_dcef_clock; > - clock_req.clock_freq_in_khz = min_clocks.dcefClock; > + clock_req.clock_freq_in_khz = min_clocks.dcefClock/10; > if (!vega12_display_clock_voltage_request(hwmgr, &clock_req)) > { > if (data->smu_features[GNLD_DS_DCEFCLK].supported) > PP_ASSERT_WITH_CODE( > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
