Looks like the patches should be reordered, e.g. patch #2 should be the
last.
Apart from that Reviewed-by: Christian König <[email protected]>.
Regards,
Christian.
Am 09.07.2018 um 18:54 schrieb Deucher, Alexander:
Series is:
Reviewed-by: Alex Deucher <[email protected]>
------------------------------------------------------------------------
*From:* amd-gfx <[email protected]> on behalf of
Leo Liu <[email protected]>
*Sent:* Monday, July 9, 2018 12:11:38 PM
*To:* [email protected]
*Cc:* Liu, Leo
*Subject:* [PATCH 3/3] drm/amdgpu: move cache window setup after power
and clock resume
To make register read/write reliable. Along with the previous patch,
VCN will work with dpm disabled case.
Signed-off-by: Leo Liu <[email protected]>
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index b82c92084b6f..ca4265bc10b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -600,12 +600,12 @@ static int vcn_v1_0_start(struct amdgpu_device
*adev)
/* disable byte swapping */
lmi_swap_cntl = 0;
- vcn_v1_0_mc_resume(adev);
-
vcn_1_0_disable_static_power_gating(adev);
/* disable clock gating */
vcn_v1_0_disable_clock_gating(adev);
+ vcn_v1_0_mc_resume(adev);
+
/* disable interupt */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
~UVD_MASTINT_EN__VCPU_EN_MASK);
--
2.17.1
_______________________________________________
amd-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
