On 2018-07-12 09:58 AM, Alex Deucher wrote:
> On Thu, Jul 12, 2018 at 9:46 AM, Harry Wentland <harry.wentl...@amd.com>
> wrote:
>> Fixing Nicholas's email.
>>
>> On 2018-07-12 09:36 AM, Harry Wentland wrote:
>>> The driver is expecting clock frequency in kHz, while SMU returns
>>> the values in 10kHz, which causes the bandwidth validation to fail
>>>
>>> 4.18 has the faulty clock assignment in pp_to_dc_clock_levels_with_latency
>>> only, which is only used by Vega. Make sure we multiply these values
>>> by 10 here, as we do for other ASICs as powerplay assigned them
>>> wrong. 4.19 has the proper fix in powerplay.
>>>
>>> Signed-off-by: Mikita Lipski <mikita.lip...@amd.com>
>>> Signed-off-by: Harry Wentland <harry.wentl...@amd.com>
>>> ---
>>>
>>> Alex, please pull this into drm-fixes-4.18.
>
> I assume this fixes:
> https://bugs.freedesktop.org/show_bug.cgi?id=107082 ?
>
Correct, sending v2.
Harry
> Thanks,
>
> Alex
>
>>>
>>> Harry
>>>
>>> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 5 +++--
>>> 1 file changed, 3 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
>>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
>>> index 5a3346124a01..5a2e952c5bea 100644
>>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
>>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
>>> @@ -255,8 +255,9 @@ static void pp_to_dc_clock_levels_with_latency(
>>> DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
>>>
>>> for (i = 0; i < clk_level_info->num_levels; i++) {
>>> - DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
>>> - clk_level_info->data[i].clocks_in_khz =
>>> pp_clks->data[i].clocks_in_khz;
>>> + DRM_DEBUG("DM_PPLIB:\t %d in 10kHz\n",
>>> pp_clks->data[i].clocks_in_khz);
>>> + /* translate 10kHz to kHz */
>>> + clk_level_info->data[i].clocks_in_khz =
>>> pp_clks->data[i].clocks_in_khz * 10;
>>> clk_level_info->data[i].latency_in_us =
>>> pp_clks->data[i].latency_in_us;
>>> }
>>> }
>>>
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