need to clear ib preempt in a proper time
Signed-off-by: Rex Zhu <[email protected]>
---
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 13 +++++++++++++
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 ++++++++++++
2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index e321d9d..de280d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -484,7 +484,11 @@ static void sdma_v3_0_ring_emit_hdp_flush(struct
amdgpu_ring *ring)
static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64
seq,
unsigned flags)
{
+ struct amdgpu_device *adev = ring->adev;
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
+ bool clear_preempt = flags & AMDGPU_FENCE_FLAG_CLEAR_PREEMPT;
+ u32 index = 0;
+
/* write the fence */
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
amdgpu_ring_write(ring, lower_32_bits(addr));
@@ -500,6 +504,15 @@ static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring
*ring, u64 addr, u64 se
amdgpu_ring_write(ring, upper_32_bits(seq));
}
+ if (!amdgpu_sriov_vf(adev) && adev->gpu_preemption && clear_preempt) {
+ if (!amdgpu_get_sdma_index(ring, &index)) {
+ amdgpu_ring_alloc(ring, 4);
+ amdgpu_ring_emit_wreg(ring, index == 0 ?
+ mmSDMA0_GFX_PREEMPT :
+ mmSDMA1_GFX_PREEMPT, 0);
+ }
+ }
+
/* generate an interrupt */
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3eeac44..33bdeeb 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -591,7 +591,10 @@ static void sdma_v4_0_ring_emit_hdp_flush(struct
amdgpu_ring *ring)
static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64
seq,
unsigned flags)
{
+ struct amdgpu_device *adev = ring->adev;
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
+ bool clear_preempt = flags & AMDGPU_FENCE_FLAG_CLEAR_PREEMPT;
+ u32 index = 0;
/* write the fence */
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
/* zero in first two bits */
@@ -611,6 +614,15 @@ static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring
*ring, u64 addr, u64 se
amdgpu_ring_write(ring, upper_32_bits(seq));
}
+ if (!amdgpu_sriov_vf(adev) && adev->gpu_preemption && clear_preempt) {
+ if (!amdgpu_get_sdma_index(ring, &index)) {
+ amdgpu_ring_alloc(ring, 4);
+ amdgpu_ring_emit_wreg(ring, index == 0 ?
+ mmSDMA0_GFX_PREEMPT :
+ mmSDMA1_GFX_PREEMPT, 0);
+ }
+ }
+
/* generate an interrupt */
amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
--
1.9.1
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