So that they can be shared in PSP widely.

Change-Id: Icec5d23db2c1f8241f6bdff371e6cde65ffdb101
Signed-off-by: Evan Quan <evan.q...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/Makefile     |   3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c |  36 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h |  16 --
 drivers/gpu/drm/amd/amdgpu/psp_cmn.c    | 289 ++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/psp_cmn.h    |  41 ++++
 drivers/gpu/drm/amd/amdgpu/psp_ring.c   |   9 +-
 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c  | 126 +----------
 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c  | 250 +-------------------
 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c   | 243 +-------------------
 9 files changed, 366 insertions(+), 647 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_cmn.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_cmn.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index bdcf0d4338f8..fe27d6038da9 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -91,7 +91,8 @@ amdgpu-y += \
        psp_v3_1.o \
        psp_v10_0.o \
        psp_v11_0.o \
-       psp_ring.o
+       psp_ring.o \
+       psp_cmn.o
 
 # add SMC block
 amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 38398f0c10c9..d1ccc6ea7607 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -47,6 +47,20 @@
                (psp)->funcs->submit_cmd_buf((psp), (ucode), (cmd), (fence_mc))
 #define psp_support_vmr_ring(psp) \
                ((psp)->funcs->support_vmr_ring ? 
(psp)->funcs->support_vmr_ring((psp)) : false)
+#define psp_compare_sram_data(psp, ucode, type) \
+               (psp)->funcs->compare_sram_data((psp), (ucode), (type))
+#define psp_init_microcode(psp) \
+               ((psp)->funcs->init_microcode ? 
(psp)->funcs->init_microcode((psp)) : 0)
+#define psp_bootloader_load_sysdrv(psp) \
+               ((psp)->funcs->bootloader_load_sysdrv ? 
(psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
+#define psp_bootloader_load_sos(psp) \
+               ((psp)->funcs->bootloader_load_sos ? 
(psp)->funcs->bootloader_load_sos((psp)) : 0)
+#define psp_smu_reload_quirk(psp) \
+               ((psp)->funcs->smu_reload_quirk ? 
(psp)->funcs->smu_reload_quirk((psp)) : false)
+#define psp_mode1_reset(psp) \
+               ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : 
false)
+#define amdgpu_psp_check_fw_loading_status(adev, i) \
+               (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
 
 static void psp_set_funcs(struct amdgpu_device *adev);
 
@@ -110,28 +124,6 @@ static int psp_sw_fini(void *handle)
        return 0;
 }
 
-int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
-                uint32_t reg_val, uint32_t mask, bool check_changed)
-{
-       uint32_t val;
-       int i;
-       struct amdgpu_device *adev = psp->adev;
-
-       for (i = 0; i < adev->usec_timeout; i++) {
-               val = RREG32(reg_index);
-               if (check_changed) {
-                       if (val != reg_val)
-                               return 0;
-               } else {
-                       if ((val & mask) == reg_val)
-                               return 0;
-               }
-               udelay(1);
-       }
-
-       return -ETIME;
-}
-
 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
                                 struct psp_gfx_cmd_resp *cmd,
                                 uint64_t tmr_mc, uint32_t size)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index c94fa444f8b7..f4438a5077b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -175,18 +175,6 @@ struct psp_xgmi_topology_info {
        struct psp_xgmi_node_info       nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
 };
 
-#define psp_compare_sram_data(psp, ucode, type) \
-               (psp)->funcs->compare_sram_data((psp), (ucode), (type))
-#define psp_init_microcode(psp) \
-               ((psp)->funcs->init_microcode ? 
(psp)->funcs->init_microcode((psp)) : 0)
-#define psp_bootloader_load_sysdrv(psp) \
-               ((psp)->funcs->bootloader_load_sysdrv ? 
(psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
-#define psp_bootloader_load_sos(psp) \
-               ((psp)->funcs->bootloader_load_sos ? 
(psp)->funcs->bootloader_load_sos((psp)) : 0)
-#define psp_smu_reload_quirk(psp) \
-               ((psp)->funcs->smu_reload_quirk ? 
(psp)->funcs->smu_reload_quirk((psp)) : false)
-#define psp_mode1_reset(psp) \
-               ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : 
false)
 #define psp_xgmi_get_node_id(psp, node_id) \
                ((psp)->funcs->xgmi_get_node_id ? 
(psp)->funcs->xgmi_get_node_id((psp), (node_id)) : -EINVAL)
 #define psp_xgmi_get_hive_id(psp, hive_id) \
@@ -198,13 +186,9 @@ struct psp_xgmi_topology_info {
                ((psp)->funcs->xgmi_set_topology_info ?  \
                (psp)->funcs->xgmi_set_topology_info((psp), (num_device), 
(topology)) : -EINVAL)
 
-#define amdgpu_psp_check_fw_loading_status(adev, i) 
(adev)->firmware.funcs->check_fw_loading_status((adev), (i))
-
 extern const struct amd_ip_funcs psp_ip_funcs;
 
 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
-extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
-                       uint32_t field_val, uint32_t mask, bool check_changed);
 
 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_cmn.c 
b/drivers/gpu/drm/amd/amdgpu/psp_cmn.c
new file mode 100644
index 000000000000..6a614c7e3b70
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/psp_cmn.c
@@ -0,0 +1,289 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "psp_cmn.h"
+#include "soc15_common.h"
+#include "mp/mp_11_0_offset.h"
+#include "mp/mp_11_0_sh_mask.h"
+#include "gc/gc_9_2_1_offset.h"
+#include "sdma0/sdma0_4_2_offset.h"
+
+int psp_cmn_wait_for(struct psp_context *psp, uint32_t reg_index,
+                uint32_t reg_val, uint32_t mask, bool check_changed)
+{
+       uint32_t val;
+       int i;
+       struct amdgpu_device *adev = psp->adev;
+
+       for (i = 0; i < adev->usec_timeout; i++) {
+               val = RREG32(reg_index);
+               if (check_changed) {
+                       if (val != reg_val)
+                               return 0;
+               } else {
+                       if ((val & mask) == reg_val)
+                               return 0;
+               }
+               udelay(1);
+       }
+
+       return -ETIME;
+}
+
+int psp_cmn_mode1_reset(struct psp_context *psp)
+{
+       struct amdgpu_device *adev = psp->adev;
+       uint32_t offset;
+       int ret;
+
+       offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
+
+       ret = psp_cmn_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
+       if (ret) {
+               DRM_ERROR("psp is not working correctly before mode1 reset!\n");
+               return -EINVAL;
+       }
+
+       /*send the mode 1 reset command*/
+       WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
+
+       msleep(500);
+
+       offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
+
+       ret = psp_cmn_wait_for(psp, offset, 0x80000000, 0x80000000, false);
+       if (ret) {
+               DRM_ERROR("psp mode 1 reset failed!\n");
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static int
+psp_cmn_sram_map(struct amdgpu_device *adev,
+                  unsigned int *sram_offset, unsigned int 
*sram_addr_reg_offset,
+                  unsigned int *sram_data_reg_offset,
+                  enum AMDGPU_UCODE_ID ucode_id)
+{
+       int ret = 0;
+
+       switch(ucode_id) {
+/* TODO: needs to confirm */
+#if 0
+       case AMDGPU_UCODE_ID_SMC:
+               *sram_offset = 0;
+               *sram_addr_reg_offset = 0;
+               *sram_data_reg_offset = 0;
+               break;
+#endif
+
+       case AMDGPU_UCODE_ID_CP_CE:
+               *sram_offset = 0x0;
+               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_CE_UCODE_ADDR);
+               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_CE_UCODE_DATA);
+               break;
+
+       case AMDGPU_UCODE_ID_CP_PFP:
+               *sram_offset = 0x0;
+               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_PFP_UCODE_ADDR);
+               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_PFP_UCODE_DATA);
+               break;
+
+       case AMDGPU_UCODE_ID_CP_ME:
+               *sram_offset = 0x0;
+               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_HYP_ME_UCODE_ADDR);
+               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_HYP_ME_UCODE_DATA);
+               break;
+
+       case AMDGPU_UCODE_ID_CP_MEC1:
+               *sram_offset = 0x10000;
+               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_MEC_ME1_UCODE_ADDR);
+               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_MEC_ME1_UCODE_DATA);
+               break;
+
+       case AMDGPU_UCODE_ID_CP_MEC2:
+               *sram_offset = 0x10000;
+               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_HYP_MEC2_UCODE_ADDR);
+               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_HYP_MEC2_UCODE_DATA);
+               break;
+
+       case AMDGPU_UCODE_ID_RLC_G:
+               *sram_offset = 0x2000;
+               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmRLC_GPM_UCODE_ADDR);
+               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmRLC_GPM_UCODE_DATA);
+               break;
+
+       case AMDGPU_UCODE_ID_SDMA0:
+               *sram_offset = 0x0;
+               *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, 
mmSDMA0_UCODE_ADDR);
+               *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, 
mmSDMA0_UCODE_DATA);
+               break;
+
+/* TODO: needs to confirm */
+#if 0
+       case AMDGPU_UCODE_ID_SDMA1:
+               *sram_offset = ;
+               *sram_addr_reg_offset = ;
+               break;
+
+       case AMDGPU_UCODE_ID_UVD:
+               *sram_offset = ;
+               *sram_addr_reg_offset = ;
+               break;
+
+       case AMDGPU_UCODE_ID_VCE:
+               *sram_offset = ;
+               *sram_addr_reg_offset = ;
+               break;
+#endif
+
+       case AMDGPU_UCODE_ID_MAXIMUM:
+       default:
+               ret = -EINVAL;
+               break;
+       }
+
+       return ret;
+}
+
+bool psp_cmn_compare_sram_data(struct psp_context *psp,
+                                       struct amdgpu_firmware_info *ucode,
+                                       enum AMDGPU_UCODE_ID ucode_type)
+{
+       int err = 0;
+       unsigned int fw_sram_reg_val = 0;
+       unsigned int fw_sram_addr_reg_offset = 0;
+       unsigned int fw_sram_data_reg_offset = 0;
+       unsigned int ucode_size;
+       uint32_t *ucode_mem = NULL;
+       struct amdgpu_device *adev = psp->adev;
+
+       err = psp_cmn_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
+                               &fw_sram_data_reg_offset, ucode_type);
+       if (err)
+               return false;
+
+       WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
+
+       ucode_size = ucode->ucode_size;
+       ucode_mem = (uint32_t *)ucode->kaddr;
+       while (!ucode_size) {
+               fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
+
+               if (*ucode_mem != fw_sram_reg_val)
+                       return false;
+
+               ucode_mem++;
+               /* 4 bytes */
+               ucode_size -= 4;
+       }
+
+       return true;
+}
+
+int psp_cmn_bootloader_load_sysdrv(struct psp_context *psp)
+{
+       int ret;
+       uint32_t psp_gfxdrv_command_reg = 0;
+       struct amdgpu_device *adev = psp->adev;
+       uint32_t sol_reg;
+
+       /* Check sOS sign of life register to confirm sys driver and sOS
+        * are already been loaded.
+        */
+       sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
+       if (sol_reg) {
+               psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
+               printk("sos fw version = 0x%x.\n", psp->sos_fw_version);
+               return 0;
+       }
+
+       /* Wait for bootloader to signify that is ready having bit 31 of 
C2PMSG_35 set to 1 */
+       ret = psp_cmn_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 
mmMP0_SMN_C2PMSG_35),
+                          0x80000000, 0x80000000, false);
+       if (ret)
+               return ret;
+
+       memset(psp->fw_pri_buf, 0, PSP_1_MEG);
+
+       /* Copy PSP System Driver binary to memory */
+       memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
+
+       /* Provide the sys driver to bootloader */
+       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
+              (uint32_t)(psp->fw_pri_mc_addr >> 20));
+       psp_gfxdrv_command_reg = 1 << 16;
+       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
+              psp_gfxdrv_command_reg);
+
+       /* there might be handshake issue with hardware which needs delay */
+       mdelay(20);
+
+       ret = psp_cmn_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 
mmMP0_SMN_C2PMSG_35),
+                          0x80000000, 0x80000000, false);
+
+       return ret;
+}
+
+int psp_cmn_bootloader_load_sos(struct psp_context *psp)
+{
+       int ret;
+       unsigned int psp_gfxdrv_command_reg = 0;
+       struct amdgpu_device *adev = psp->adev;
+       uint32_t sol_reg;
+
+       /* Check sOS sign of life register to confirm sys driver and sOS
+        * are already been loaded.
+        */
+       sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
+       if (sol_reg)
+               return 0;
+
+       /* Wait for bootloader to signify that is ready having bit 31 of 
C2PMSG_35 set to 1 */
+       ret = psp_cmn_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 
mmMP0_SMN_C2PMSG_35),
+                          0x80000000, 0x80000000, false);
+       if (ret)
+               return ret;
+
+       memset(psp->fw_pri_buf, 0, PSP_1_MEG);
+
+       /* Copy Secure OS binary to PSP memory */
+       memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
+
+       /* Provide the PSP secure OS to bootloader */
+       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
+              (uint32_t)(psp->fw_pri_mc_addr >> 20));
+       psp_gfxdrv_command_reg = 2 << 16;
+       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
+              psp_gfxdrv_command_reg);
+
+       /* there might be handshake issue with hardware which needs delay */
+       mdelay(20);
+       ret = psp_cmn_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 
mmMP0_SMN_C2PMSG_81),
+                          RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
+                          0, true);
+
+       return ret;
+}
+
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_cmn.h 
b/drivers/gpu/drm/amd/amdgpu/psp_cmn.h
new file mode 100644
index 000000000000..a1c0ad0bce72
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/psp_cmn.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __PSP_CMN_H
+#define __PSP_CMN_H
+
+#include "amdgpu_psp.h"
+
+int psp_cmn_mode1_reset(struct psp_context *psp);
+
+bool psp_cmn_compare_sram_data(struct psp_context *psp,
+                                       struct amdgpu_firmware_info *ucode,
+                                       enum AMDGPU_UCODE_ID ucode_type);
+
+int psp_cmn_bootloader_load_sysdrv(struct psp_context *psp);
+
+int psp_cmn_bootloader_load_sos(struct psp_context *psp);
+
+int psp_cmn_wait_for(struct psp_context *psp, uint32_t reg_index,
+                uint32_t reg_val, uint32_t mask, bool check_changed);
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_ring.c 
b/drivers/gpu/drm/amd/amdgpu/psp_ring.c
index c2f1ade51758..fa59e57fb11e 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_ring.c
@@ -24,6 +24,7 @@
 #include "soc15_common.h"
 #include "mp/mp_11_0_offset.h"
 #include "mp/mp_11_0_sh_mask.h"
+#include "psp_cmn.h"
 
 int psp_ring_init_ring(struct psp_context *psp,
                              enum psp_ring_type ring_type)
@@ -87,7 +88,7 @@ int psp_ring_create_ring(struct psp_context *psp,
                mdelay(20);
 
                /* Wait for response flag (bit 31) in C2PMSG_101 */
-               ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 
mmMP0_SMN_C2PMSG_101),
+               ret = psp_cmn_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 
mmMP0_SMN_C2PMSG_101),
                                   0x80000000, 0x8000FFFF, false);
 
        } else {
@@ -109,7 +110,7 @@ int psp_ring_create_ring(struct psp_context *psp,
                mdelay(20);
 
                /* Wait for response flag (bit 31) in C2PMSG_64 */
-               ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 
mmMP0_SMN_C2PMSG_64),
+               ret = psp_cmn_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 
mmMP0_SMN_C2PMSG_64),
                                   0x80000000, 0x8000FFFF, false);
        }
 
@@ -135,10 +136,10 @@ int psp_ring_stop_ring(struct psp_context *psp,
 
        /* Wait for response flag (bit 31) */
        if (psp_ring_support_vmr(psp))
-               ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 
mmMP0_SMN_C2PMSG_101),
+               ret = psp_cmn_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 
mmMP0_SMN_C2PMSG_101),
                                   0x80000000, 0x80000000, false);
        else
-               ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 
mmMP0_SMN_C2PMSG_64),
+               ret = psp_cmn_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 
mmMP0_SMN_C2PMSG_64),
                                   0x80000000, 0x80000000, false);
 
        return ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 700a766751fa..87d9560a52ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -34,6 +34,7 @@
 #include "gc/gc_9_1_offset.h"
 #include "sdma0/sdma0_4_1_offset.h"
 #include "psp_ring.h"
+#include "psp_cmn.h"
 
 MODULE_FIRMWARE("amdgpu/raven_asd.bin");
 MODULE_FIRMWARE("amdgpu/picasso_asd.bin");
@@ -90,129 +91,6 @@ static int psp_v10_0_init_microcode(struct psp_context *psp)
        return err;
 }
 
-static int
-psp_v10_0_sram_map(struct amdgpu_device *adev,
-                  unsigned int *sram_offset, unsigned int 
*sram_addr_reg_offset,
-                  unsigned int *sram_data_reg_offset,
-                  enum AMDGPU_UCODE_ID ucode_id)
-{
-       int ret = 0;
-
-       switch(ucode_id) {
-/* TODO: needs to confirm */
-#if 0
-       case AMDGPU_UCODE_ID_SMC:
-               *sram_offset = 0;
-               *sram_addr_reg_offset = 0;
-               *sram_data_reg_offset = 0;
-               break;
-#endif
-
-       case AMDGPU_UCODE_ID_CP_CE:
-               *sram_offset = 0x0;
-               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_CE_UCODE_ADDR);
-               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_CE_UCODE_DATA);
-               break;
-
-       case AMDGPU_UCODE_ID_CP_PFP:
-               *sram_offset = 0x0;
-               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_PFP_UCODE_ADDR);
-               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_PFP_UCODE_DATA);
-               break;
-
-       case AMDGPU_UCODE_ID_CP_ME:
-               *sram_offset = 0x0;
-               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_HYP_ME_UCODE_ADDR);
-               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_HYP_ME_UCODE_DATA);
-               break;
-
-       case AMDGPU_UCODE_ID_CP_MEC1:
-               *sram_offset = 0x10000;
-               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_MEC_ME1_UCODE_ADDR);
-               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_MEC_ME1_UCODE_DATA);
-               break;
-
-       case AMDGPU_UCODE_ID_CP_MEC2:
-               *sram_offset = 0x10000;
-               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_HYP_MEC2_UCODE_ADDR);
-               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_HYP_MEC2_UCODE_DATA);
-               break;
-
-       case AMDGPU_UCODE_ID_RLC_G:
-               *sram_offset = 0x2000;
-               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmRLC_GPM_UCODE_ADDR);
-               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmRLC_GPM_UCODE_DATA);
-               break;
-
-       case AMDGPU_UCODE_ID_SDMA0:
-               *sram_offset = 0x0;
-               *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, 
mmSDMA0_UCODE_ADDR);
-               *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, 
mmSDMA0_UCODE_DATA);
-               break;
-
-/* TODO: needs to confirm */
-#if 0
-       case AMDGPU_UCODE_ID_SDMA1:
-               *sram_offset = ;
-               *sram_addr_reg_offset = ;
-               break;
-
-       case AMDGPU_UCODE_ID_UVD:
-               *sram_offset = ;
-               *sram_addr_reg_offset = ;
-               break;
-
-       case AMDGPU_UCODE_ID_VCE:
-               *sram_offset = ;
-               *sram_addr_reg_offset = ;
-               break;
-#endif
-
-       case AMDGPU_UCODE_ID_MAXIMUM:
-       default:
-               ret = -EINVAL;
-               break;
-       }
-
-       return ret;
-}
-
-static bool psp_v10_0_compare_sram_data(struct psp_context *psp,
-                                       struct amdgpu_firmware_info *ucode,
-                                       enum AMDGPU_UCODE_ID ucode_type)
-{
-       int err = 0;
-       unsigned int fw_sram_reg_val = 0;
-       unsigned int fw_sram_addr_reg_offset = 0;
-       unsigned int fw_sram_data_reg_offset = 0;
-       unsigned int ucode_size;
-       uint32_t *ucode_mem = NULL;
-       struct amdgpu_device *adev = psp->adev;
-
-       err = psp_v10_0_sram_map(adev, &fw_sram_reg_val, 
&fw_sram_addr_reg_offset,
-                               &fw_sram_data_reg_offset, ucode_type);
-       if (err)
-               return false;
-
-       WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
-
-       ucode_size = ucode->ucode_size;
-       ucode_mem = (uint32_t *)ucode->kaddr;
-       while (!ucode_size) {
-               fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
-
-               if (*ucode_mem != fw_sram_reg_val)
-                       return false;
-
-               ucode_mem++;
-               /* 4 bytes */
-               ucode_size -= 4;
-       }
-
-       return true;
-}
-
-
 static int psp_v10_0_mode1_reset(struct psp_context *psp)
 {
        DRM_INFO("psp mode 1 reset not supported now! \n");
@@ -227,7 +105,7 @@ static const struct psp_funcs psp_v10_0_funcs = {
        .ring_destroy = psp_ring_destroy_ring,
        .prep_cmd_buf = psp_ring_prep_cmd_buf,
        .submit_cmd_buf = psp_ring_submit_cmd_buf,
-       .compare_sram_data = psp_v10_0_compare_sram_data,
+       .compare_sram_data = psp_cmn_compare_sram_data,
        .mode1_reset = psp_v10_0_mode1_reset,
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 43487d97a0cd..1dc62ec4e64b 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -33,6 +33,7 @@
 #include "sdma0/sdma0_4_0_offset.h"
 #include "nbio/nbio_7_4_offset.h"
 #include "psp_ring.h"
+#include "psp_cmn.h"
 
 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
 MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
@@ -129,247 +130,6 @@ static int psp_v11_0_init_microcode(struct psp_context 
*psp)
        return err;
 }
 
-static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
-{
-       int ret;
-       uint32_t psp_gfxdrv_command_reg = 0;
-       struct amdgpu_device *adev = psp->adev;
-       uint32_t sol_reg;
-
-       /* Check sOS sign of life register to confirm sys driver and sOS
-        * are already been loaded.
-        */
-       sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
-       if (sol_reg) {
-               psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
-               printk("sos fw version = 0x%x.\n", psp->sos_fw_version);
-               return 0;
-       }
-
-       /* Wait for bootloader to signify that is ready having bit 31 of 
C2PMSG_35 set to 1 */
-       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
-                          0x80000000, 0x80000000, false);
-       if (ret)
-               return ret;
-
-       memset(psp->fw_pri_buf, 0, PSP_1_MEG);
-
-       /* Copy PSP System Driver binary to memory */
-       memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
-
-       /* Provide the sys driver to bootloader */
-       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
-              (uint32_t)(psp->fw_pri_mc_addr >> 20));
-       psp_gfxdrv_command_reg = 1 << 16;
-       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
-              psp_gfxdrv_command_reg);
-
-       /* there might be handshake issue with hardware which needs delay */
-       mdelay(20);
-
-       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
-                          0x80000000, 0x80000000, false);
-
-       return ret;
-}
-
-static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
-{
-       int ret;
-       unsigned int psp_gfxdrv_command_reg = 0;
-       struct amdgpu_device *adev = psp->adev;
-       uint32_t sol_reg;
-
-       /* Check sOS sign of life register to confirm sys driver and sOS
-        * are already been loaded.
-        */
-       sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
-       if (sol_reg)
-               return 0;
-
-       /* Wait for bootloader to signify that is ready having bit 31 of 
C2PMSG_35 set to 1 */
-       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
-                          0x80000000, 0x80000000, false);
-       if (ret)
-               return ret;
-
-       memset(psp->fw_pri_buf, 0, PSP_1_MEG);
-
-       /* Copy Secure OS binary to PSP memory */
-       memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
-
-       /* Provide the PSP secure OS to bootloader */
-       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
-              (uint32_t)(psp->fw_pri_mc_addr >> 20));
-       psp_gfxdrv_command_reg = 2 << 16;
-       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
-              psp_gfxdrv_command_reg);
-
-       /* there might be handshake issue with hardware which needs delay */
-       mdelay(20);
-       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
-                          RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
-                          0, true);
-
-       return ret;
-}
-
-static int
-psp_v11_0_sram_map(struct amdgpu_device *adev,
-                 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
-                 unsigned int *sram_data_reg_offset,
-                 enum AMDGPU_UCODE_ID ucode_id)
-{
-       int ret = 0;
-
-       switch (ucode_id) {
-/* TODO: needs to confirm */
-#if 0
-       case AMDGPU_UCODE_ID_SMC:
-               *sram_offset = 0;
-               *sram_addr_reg_offset = 0;
-               *sram_data_reg_offset = 0;
-               break;
-#endif
-
-       case AMDGPU_UCODE_ID_CP_CE:
-               *sram_offset = 0x0;
-               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_CE_UCODE_ADDR);
-               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_CE_UCODE_DATA);
-               break;
-
-       case AMDGPU_UCODE_ID_CP_PFP:
-               *sram_offset = 0x0;
-               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_PFP_UCODE_ADDR);
-               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_PFP_UCODE_DATA);
-               break;
-
-       case AMDGPU_UCODE_ID_CP_ME:
-               *sram_offset = 0x0;
-               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_HYP_ME_UCODE_ADDR);
-               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_HYP_ME_UCODE_DATA);
-               break;
-
-       case AMDGPU_UCODE_ID_CP_MEC1:
-               *sram_offset = 0x10000;
-               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_MEC_ME1_UCODE_ADDR);
-               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_MEC_ME1_UCODE_DATA);
-               break;
-
-       case AMDGPU_UCODE_ID_CP_MEC2:
-               *sram_offset = 0x10000;
-               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_HYP_MEC2_UCODE_ADDR);
-               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_HYP_MEC2_UCODE_DATA);
-               break;
-
-       case AMDGPU_UCODE_ID_RLC_G:
-               *sram_offset = 0x2000;
-               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmRLC_GPM_UCODE_ADDR);
-               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmRLC_GPM_UCODE_DATA);
-               break;
-
-       case AMDGPU_UCODE_ID_SDMA0:
-               *sram_offset = 0x0;
-               *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, 
mmSDMA0_UCODE_ADDR);
-               *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, 
mmSDMA0_UCODE_DATA);
-               break;
-
-/* TODO: needs to confirm */
-#if 0
-       case AMDGPU_UCODE_ID_SDMA1:
-               *sram_offset = ;
-               *sram_addr_reg_offset = ;
-               break;
-
-       case AMDGPU_UCODE_ID_UVD:
-               *sram_offset = ;
-               *sram_addr_reg_offset = ;
-               break;
-
-       case AMDGPU_UCODE_ID_VCE:
-               *sram_offset = ;
-               *sram_addr_reg_offset = ;
-               break;
-#endif
-
-       case AMDGPU_UCODE_ID_MAXIMUM:
-       default:
-               ret = -EINVAL;
-               break;
-       }
-
-       return ret;
-}
-
-static bool psp_v11_0_compare_sram_data(struct psp_context *psp,
-                                      struct amdgpu_firmware_info *ucode,
-                                      enum AMDGPU_UCODE_ID ucode_type)
-{
-       int err = 0;
-       unsigned int fw_sram_reg_val = 0;
-       unsigned int fw_sram_addr_reg_offset = 0;
-       unsigned int fw_sram_data_reg_offset = 0;
-       unsigned int ucode_size;
-       uint32_t *ucode_mem = NULL;
-       struct amdgpu_device *adev = psp->adev;
-
-       err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, 
&fw_sram_addr_reg_offset,
-                               &fw_sram_data_reg_offset, ucode_type);
-       if (err)
-               return false;
-
-       WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
-
-       ucode_size = ucode->ucode_size;
-       ucode_mem = (uint32_t *)ucode->kaddr;
-       while (ucode_size) {
-               fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
-
-               if (*ucode_mem != fw_sram_reg_val)
-                       return false;
-
-               ucode_mem++;
-               /* 4 bytes */
-               ucode_size -= 4;
-       }
-
-       return true;
-}
-
-static int psp_v11_0_mode1_reset(struct psp_context *psp)
-{
-       int ret;
-       uint32_t offset;
-       struct amdgpu_device *adev = psp->adev;
-
-       offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
-
-       ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
-
-       if (ret) {
-               DRM_INFO("psp is not working correctly before mode1 reset!\n");
-               return -EINVAL;
-       }
-
-       /*send the mode 1 reset command*/
-       WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
-
-       msleep(500);
-
-       offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
-
-       ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
-
-       if (ret) {
-               DRM_INFO("psp mode 1 reset failed!\n");
-               return -EINVAL;
-       }
-
-       DRM_INFO("psp mode1 reset succeed \n");
-
-       return 0;
-}
-
 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is 
ready.
  * For now, return success and hack the hive_id so high level code can
  * start testing
@@ -489,8 +249,6 @@ static int psp_v11_0_xgmi_get_node_id(struct psp_context 
*psp, uint64_t *node_id
 
 static const struct psp_funcs psp_v11_0_funcs = {
        .init_microcode = psp_v11_0_init_microcode,
-       .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
-       .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
        .ring_init = psp_ring_init_ring,
        .ring_create = psp_ring_create_ring,
        .ring_stop = psp_ring_stop_ring,
@@ -498,8 +256,10 @@ static const struct psp_funcs psp_v11_0_funcs = {
        .prep_cmd_buf = psp_ring_prep_cmd_buf,
        .submit_cmd_buf = psp_ring_submit_cmd_buf,
        .support_vmr_ring = psp_ring_support_vmr,
-       .compare_sram_data = psp_v11_0_compare_sram_data,
-       .mode1_reset = psp_v11_0_mode1_reset,
+       .bootloader_load_sysdrv = psp_cmn_bootloader_load_sysdrv,
+       .bootloader_load_sos = psp_cmn_bootloader_load_sos,
+       .compare_sram_data = psp_cmn_compare_sram_data,
+       .mode1_reset = psp_cmn_mode1_reset,
        .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info,
        .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info,
        .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id,
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c 
b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index b74dd556a573..a013c3ae114b 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -37,6 +37,7 @@
 #include "sdma0/sdma0_4_0_offset.h"
 #include "nbio/nbio_6_1_offset.h"
 #include "psp_ring.h"
+#include "psp_cmn.h"
 
 MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
 MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
@@ -119,47 +120,6 @@ static int psp_v3_1_init_microcode(struct psp_context *psp)
        return err;
 }
 
-static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
-{
-       int ret;
-       uint32_t psp_gfxdrv_command_reg = 0;
-       struct amdgpu_device *adev = psp->adev;
-       uint32_t sol_reg;
-
-       /* Check sOS sign of life register to confirm sys driver and sOS
-        * are already been loaded.
-        */
-       sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
-       if (sol_reg)
-               return 0;
-
-       /* Wait for bootloader to signify that is ready having bit 31 of 
C2PMSG_35 set to 1 */
-       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
-                          0x80000000, 0x80000000, false);
-       if (ret)
-               return ret;
-
-       memset(psp->fw_pri_buf, 0, PSP_1_MEG);
-
-       /* Copy PSP System Driver binary to memory */
-       memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
-
-       /* Provide the sys driver to bootloader */
-       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
-              (uint32_t)(psp->fw_pri_mc_addr >> 20));
-       psp_gfxdrv_command_reg = 1 << 16;
-       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
-              psp_gfxdrv_command_reg);
-
-       /* there might be handshake issue with hardware which needs delay */
-       mdelay(20);
-
-       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
-                          0x80000000, 0x80000000, false);
-
-       return ret;
-}
-
 static bool psp_v3_1_match_version(struct amdgpu_device *adev, uint32_t ver)
 {
        int i;
@@ -181,45 +141,14 @@ static bool psp_v3_1_match_version(struct amdgpu_device 
*adev, uint32_t ver)
 
 static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
 {
-       int ret;
-       unsigned int psp_gfxdrv_command_reg = 0;
        struct amdgpu_device *adev = psp->adev;
-       uint32_t sol_reg, ver;
-
-       /* Check sOS sign of life register to confirm sys driver and sOS
-        * are already been loaded.
-        */
-       sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
-       if (sol_reg) {
-               psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
-               printk("sos fw version = 0x%x.\n", psp->sos_fw_version);
-               return 0;
-       }
+       uint32_t ver;
+       int ret;
 
-       /* Wait for bootloader to signify that is ready having bit 31 of 
C2PMSG_35 set to 1 */
-       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
-                          0x80000000, 0x80000000, false);
+       ret = psp_cmn_bootloader_load_sos(psp);
        if (ret)
                return ret;
 
-       memset(psp->fw_pri_buf, 0, PSP_1_MEG);
-
-       /* Copy Secure OS binary to PSP memory */
-       memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
-
-       /* Provide the PSP secure OS to bootloader */
-       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
-              (uint32_t)(psp->fw_pri_mc_addr >> 20));
-       psp_gfxdrv_command_reg = 2 << 16;
-       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
-              psp_gfxdrv_command_reg);
-
-       /* there might be handshake issue with hardware which needs delay */
-       mdelay(20);
-       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
-                          RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
-                          0, true);
-
        ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
        if (!psp_v3_1_match_version(adev, ver))
                DRM_WARN("SOS version doesn't match\n");
@@ -227,128 +156,6 @@ static int psp_v3_1_bootloader_load_sos(struct 
psp_context *psp)
        return ret;
 }
 
-static int
-psp_v3_1_sram_map(struct amdgpu_device *adev,
-                 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
-                 unsigned int *sram_data_reg_offset,
-                 enum AMDGPU_UCODE_ID ucode_id)
-{
-       int ret = 0;
-
-       switch(ucode_id) {
-/* TODO: needs to confirm */
-#if 0
-       case AMDGPU_UCODE_ID_SMC:
-               *sram_offset = 0;
-               *sram_addr_reg_offset = 0;
-               *sram_data_reg_offset = 0;
-               break;
-#endif
-
-       case AMDGPU_UCODE_ID_CP_CE:
-               *sram_offset = 0x0;
-               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_CE_UCODE_ADDR);
-               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_CE_UCODE_DATA);
-               break;
-
-       case AMDGPU_UCODE_ID_CP_PFP:
-               *sram_offset = 0x0;
-               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_PFP_UCODE_ADDR);
-               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_PFP_UCODE_DATA);
-               break;
-
-       case AMDGPU_UCODE_ID_CP_ME:
-               *sram_offset = 0x0;
-               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_HYP_ME_UCODE_ADDR);
-               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_HYP_ME_UCODE_DATA);
-               break;
-
-       case AMDGPU_UCODE_ID_CP_MEC1:
-               *sram_offset = 0x10000;
-               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_MEC_ME1_UCODE_ADDR);
-               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_MEC_ME1_UCODE_DATA);
-               break;
-
-       case AMDGPU_UCODE_ID_CP_MEC2:
-               *sram_offset = 0x10000;
-               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_HYP_MEC2_UCODE_ADDR);
-               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmCP_HYP_MEC2_UCODE_DATA);
-               break;
-
-       case AMDGPU_UCODE_ID_RLC_G:
-               *sram_offset = 0x2000;
-               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmRLC_GPM_UCODE_ADDR);
-               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, 
mmRLC_GPM_UCODE_DATA);
-               break;
-
-       case AMDGPU_UCODE_ID_SDMA0:
-               *sram_offset = 0x0;
-               *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, 
mmSDMA0_UCODE_ADDR);
-               *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, 
mmSDMA0_UCODE_DATA);
-               break;
-
-/* TODO: needs to confirm */
-#if 0
-       case AMDGPU_UCODE_ID_SDMA1:
-               *sram_offset = ;
-               *sram_addr_reg_offset = ;
-               break;
-
-       case AMDGPU_UCODE_ID_UVD:
-               *sram_offset = ;
-               *sram_addr_reg_offset = ;
-               break;
-
-       case AMDGPU_UCODE_ID_VCE:
-               *sram_offset = ;
-               *sram_addr_reg_offset = ;
-               break;
-#endif
-
-       case AMDGPU_UCODE_ID_MAXIMUM:
-       default:
-               ret = -EINVAL;
-               break;
-       }
-
-       return ret;
-}
-
-static bool psp_v3_1_compare_sram_data(struct psp_context *psp,
-                                      struct amdgpu_firmware_info *ucode,
-                                      enum AMDGPU_UCODE_ID ucode_type)
-{
-       int err = 0;
-       unsigned int fw_sram_reg_val = 0;
-       unsigned int fw_sram_addr_reg_offset = 0;
-       unsigned int fw_sram_data_reg_offset = 0;
-       unsigned int ucode_size;
-       uint32_t *ucode_mem = NULL;
-       struct amdgpu_device *adev = psp->adev;
-
-       err = psp_v3_1_sram_map(adev, &fw_sram_reg_val, 
&fw_sram_addr_reg_offset,
-                               &fw_sram_data_reg_offset, ucode_type);
-       if (err)
-               return false;
-
-       WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
-
-       ucode_size = ucode->ucode_size;
-       ucode_mem = (uint32_t *)ucode->kaddr;
-       while (ucode_size) {
-               fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
-
-               if (*ucode_mem != fw_sram_reg_val)
-                       return false;
-
-               ucode_mem++;
-               /* 4 bytes */
-               ucode_size -= 4;
-       }
-
-       return true;
-}
-
 static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
 {
        struct amdgpu_device *adev = psp->adev;
@@ -360,53 +167,19 @@ static bool psp_v3_1_smu_reload_quirk(struct psp_context 
*psp)
        return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : 
false;
 }
 
-static int psp_v3_1_mode1_reset(struct psp_context *psp)
-{
-       int ret;
-       uint32_t offset;
-       struct amdgpu_device *adev = psp->adev;
-
-       offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
-
-       ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
-
-       if (ret) {
-               DRM_INFO("psp is not working correctly before mode1 reset!\n");
-               return -EINVAL;
-       }
-
-       /*send the mode 1 reset command*/
-       WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
-
-       msleep(500);
-
-       offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
-
-       ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
-
-       if (ret) {
-               DRM_INFO("psp mode 1 reset failed!\n");
-               return -EINVAL;
-       }
-
-       DRM_INFO("psp mode1 reset succeed \n");
-
-       return 0;
-}
-
 static const struct psp_funcs psp_v3_1_funcs = {
        .init_microcode = psp_v3_1_init_microcode,
-       .bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv,
-       .bootloader_load_sos = psp_v3_1_bootloader_load_sos,
        .ring_init = psp_ring_init_ring,
        .ring_create = psp_ring_create_ring,
        .ring_stop = psp_ring_stop_ring,
        .ring_destroy = psp_ring_destroy_ring,
        .prep_cmd_buf = psp_ring_prep_cmd_buf,
        .submit_cmd_buf = psp_ring_submit_cmd_buf,
-       .compare_sram_data = psp_v3_1_compare_sram_data,
+       .bootloader_load_sysdrv = psp_cmn_bootloader_load_sysdrv,
+       .bootloader_load_sos = psp_v3_1_bootloader_load_sos,
+       .compare_sram_data = psp_cmn_compare_sram_data,
        .smu_reload_quirk = psp_v3_1_smu_reload_quirk,
-       .mode1_reset = psp_v3_1_mode1_reset,
+       .mode1_reset = psp_cmn_mode1_reset,
 };
 
 void psp_v3_1_set_psp_funcs(struct psp_context *psp)
-- 
2.20.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Reply via email to