Am 12.02.19 um 15:05 schrieb Colin King:
> From: Colin Ian King <colin.k...@canonical.com>
>
> There are several statements that are incorrectly indented. Fix these.
>
> Signed-off-by: Colin Ian King <colin.k...@canonical.com>
Reviewed-by: Christian König <christian.koe...@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/si.c | 2 +-
> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c | 2 +-
> drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 2 +-
> 6 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index bc62bf41b7e9..b65e18101108 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -207,7 +207,7 @@ int amdgpu_driver_load_kms(struct drm_device *dev,
> unsigned long flags)
> if (!r) {
> acpi_status = amdgpu_acpi_init(adev);
> if (acpi_status)
> - dev_dbg(&dev->pdev->dev,
> + dev_dbg(&dev->pdev->dev,
> "Error during ACPI methods call\n");
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index db443ec53d3a..bea32f076b91 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -2980,7 +2980,7 @@ static int dce_v6_0_pageflip_irq(struct amdgpu_device
> *adev,
> struct amdgpu_irq_src *source,
> struct amdgpu_iv_entry *entry)
> {
> - unsigned long flags;
> + unsigned long flags;
> unsigned crtc_id;
> struct amdgpu_crtc *amdgpu_crtc;
> struct amdgpu_flip_work *works;
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> index 221f26e50322..c69d51598cfe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> @@ -32,7 +32,7 @@
>
> static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
> {
> - u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
> + u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
>
> tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
> tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
> diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
> index 79c1a9bbcc21..9d8df68893b9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si.c
> @@ -1436,7 +1436,7 @@ static int si_common_early_init(void *handle)
> AMD_CG_SUPPORT_UVD_MGCG |
> AMD_CG_SUPPORT_HDP_LS |
> AMD_CG_SUPPORT_HDP_MGCG;
> - adev->pg_flags = 0;
> + adev->pg_flags = 0;
> adev->external_rev_id = (adev->rev_id == 0) ? 1 :
> (adev->rev_id == 1) ? 5 : 6;
> break;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
> index d138ddae563d..58f5589aaf12 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
> @@ -1211,7 +1211,7 @@ int smu7_power_control_set_level(struct pp_hwmgr *hwmgr)
> hwmgr->platform_descriptor.TDPAdjustment :
> (-1 * hwmgr->platform_descriptor.TDPAdjustment);
>
> - if (hwmgr->chip_id > CHIP_TONGA)
> + if (hwmgr->chip_id > CHIP_TONGA)
> target_tdp = ((100 + adjust_percent) *
> (int)(cac_table->usTDP * 256)) / 100;
> else
> target_tdp = ((100 + adjust_percent) *
> (int)(cac_table->usConfigurableTDP * 256)) / 100;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> index 0769b1ec562b..aad79affb081 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> @@ -3456,7 +3456,7 @@ static int vega20_apply_clocks_adjust_rules(struct
> pp_hwmgr *hwmgr)
> disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
> !hwmgr->display_config->multi_monitor_in_sync) ||
> vblank_too_short;
> - latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
> + latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
>
> /* gfxclk */
> dpm_table = &(data->dpm_table.gfx_table);
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