We should ensure mqd data take effect when gpu reset.
Otherwise, it will rasie ring ib tests failure.
Signed-off-by: Yintian Tao <yt...@amd.com>
Signed-off-by: Monk Liu <monk....@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 2e9cac1..bea641d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3123,6 +3123,8 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring
*ring)
if (adev->gfx.mec.mqd_backup[mqd_idx])
memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx],
sizeof(struct v9_mqd_allocation));
+ /* clean gpu table status */
+ amdgpu_gmc_flush_gpu_tlb(adev, 0, 0);
/* reset ring buffer */
ring->wptr = 0;
amdgpu_ring_clear_ring(ring);
@@ -3147,6 +3149,8 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring
*ring)
memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd,
sizeof(struct v9_mqd_allocation));
}
+ /* make sure mqd data landed into VRAM */
+ amdgpu_asic_flush_hdp(adev, NULL);
return 0;
}
--
2.7.4
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