From: Jack Xiao <[email protected]>

MP1 cannot access clock IP during MP1 FW reload, disable PLL
shutdown as a workaround.

Signed-off-by: Jack Xiao <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 9fb894fec3d3..8030c7a7edae 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -383,10 +383,14 @@ static int navi10_append_powerplay_table(struct 
smu_context *smu)
        /* Mvdd Svi2 Div Ratio Setting */
        smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
 
-       if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+       if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
                *(uint64_t *)smc_pptable->FeaturesToRun |= 
FEATURE_MASK(FEATURE_GFX_SS_BIT)
                                        | FEATURE_MASK(FEATURE_GFXOFF_BIT);
 
+               /* TODO: remove it once SMU fw fix it */
+               smc_pptable->DebugOverrides |= 
DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
+       }
+
        return 0;
 }
 
-- 
2.20.1

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