From: Harry Wentland <harry.wentl...@amd.com>
Add support to program DCN2 VMID (Virtual Memory Support)
Signed-off-by: Harry Wentland <harry.wentl...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c | 62 +++++++++++++
.../gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h | 91 +++++++++++++++++++
2 files changed, 153 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c
new file mode 100644
index 000000000000..50953c0bd4e3
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dcn20_vmid.h"
+#include "reg_helper.h"
+
+#define REG(reg)\
+ vmid->regs->reg
+
+#define CTX \
+ vmid->ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+ vmid->shifts->field_name, vmid->masks->field_name
+
+void dcn20_vmid_setup(struct dcn20_vmid *vmid, const struct
dcn_vmid_page_table_config *config)
+{
+ REG_SET(PAGE_TABLE_START_ADDR_HI32, 0,
+ VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4,
(config->page_table_start_addr >> 32) & 0xF);
+ REG_SET(PAGE_TABLE_START_ADDR_LO32, 0,
+ VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32,
config->page_table_start_addr & 0xFFFFFFFF);
+
+ REG_SET(PAGE_TABLE_END_ADDR_HI32, 0,
+ VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4,
(config->page_table_end_addr >> 32) & 0xF);
+ REG_SET(PAGE_TABLE_END_ADDR_LO32, 0,
+ VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32,
config->page_table_end_addr & 0xFFFFFFFF);
+
+ REG_SET_2(CNTL, 0,
+ VM_CONTEXT0_PAGE_TABLE_DEPTH, config->depth,
+ VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, config->block_size);
+}
+
+void dcn20_vmid_set_ptb(struct dcn20_vmid *vmid, uint64_t base)
+{
+ REG_SET(PAGE_TABLE_BASE_ADDR_HI32, 0,
+ VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, (base >> 32) &
0xFFFFFFFF);
+ REG_SET(PAGE_TABLE_BASE_ADDR_LO32, 0,
+ VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, base &
0xFFFFFFFF);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h
new file mode 100644
index 000000000000..9c2f7016af2a
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef DAL_DC_DCN20_DCN20_VMID_H_
+#define DAL_DC_DCN20_DCN20_VMID_H_
+
+#include "vmid.h"
+
+#define BASE_INNER(seg) \
+ DCE_BASE__INST0_SEG ## seg
+
+#define BASE(seg) \
+ BASE_INNER(seg)
+
+#define SRI(reg_name, block, id)\
+ .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+ mm ## block ## id ## _ ## reg_name
+
+#define SF(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
+
+#define DCN20_VMID_REG_LIST(id)\
+ SRI(CNTL, DCN_VM_CONTEXT, id),\
+ SRI(PAGE_TABLE_BASE_ADDR_HI32, DCN_VM_CONTEXT, id),\
+ SRI(PAGE_TABLE_BASE_ADDR_LO32, DCN_VM_CONTEXT, id),\
+ SRI(PAGE_TABLE_START_ADDR_HI32, DCN_VM_CONTEXT, id),\
+ SRI(PAGE_TABLE_START_ADDR_LO32, DCN_VM_CONTEXT, id),\
+ SRI(PAGE_TABLE_END_ADDR_HI32, DCN_VM_CONTEXT, id),\
+ SRI(PAGE_TABLE_END_ADDR_LO32, DCN_VM_CONTEXT, id)
+
+#define DCN20_VMID_MASK_SH_LIST(mask_sh)\
+ SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_DEPTH, mask_sh),\
+ SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, mask_sh),\
+ SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
+ SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
+ SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
+ SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32, mask_sh),\
+ SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
+ SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32, mask_sh)
+
+#define DCN20_VMID_REG_FIELD_LIST(type)\
+ type VM_CONTEXT0_PAGE_TABLE_DEPTH;\
+ type VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE;\
+ type VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32;\
+ type VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32;\
+ type VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4;\
+ type VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32;\
+ type VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4;\
+ type VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32
+
+struct dcn20_vmid_shift {
+ DCN20_VMID_REG_FIELD_LIST(uint8_t);
+};
+
+struct dcn20_vmid_mask {
+ DCN20_VMID_REG_FIELD_LIST(uint32_t);
+};
+
+struct dcn20_vmid {
+ struct dc_context *ctx;
+ const struct dcn_vmid_registers *regs;
+ const struct dcn20_vmid_shift *shifts;
+ const struct dcn20_vmid_mask *masks;
+};
+
+void dcn20_vmid_setup(struct dcn20_vmid *vmid, const struct
dcn_vmid_page_table_config *config);
+void dcn20_vmid_set_ptb(struct dcn20_vmid *vmid, uint64_t base);
+
+#endif /* DAL_DC_DCN20_DCN20_VMID_H_ */
--
2.20.1
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