From: Jun Lei <jun....@amd.com>
[why]
current DML logic uses currently trained setting for number
of dp lanes in DML calculations. this is obviously flawed since
just because 1 lane is in use doesn't mean only 1 lane can be used
this causes mode validation to fail depending on current state,
which is incorrect
[how]
DML should always assume 4 lanes are available. validation of
bandwidth is not supposed to be handled by DML, since we do
link validation without DML already
also, DML is expecting there to be a copy of the max state, this
state is removed when update_bounding_box is called to update
actual SKU clocks. fix this as well by duping last state.
Signed-off-by: Jun Lei <jun....@amd.com>
Reviewed-by: Dmytro Laktyushkin <dmytro.laktyush...@amd.com>
Acked-by: Bhawanpreet Lakha <bhawanpreet.la...@amd.com>
Acked-by: Eric Yang <eric.ya...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index caebf4746475..266d2ea50882 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1619,7 +1619,6 @@ int dcn20_populate_dml_pipes_from_context(
for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
struct dc_crtc_timing *timing =
&res_ctx->pipe_ctx[i].stream->timing;
- struct dc_link *link;
if (!res_ctx->pipe_ctx[i].stream)
continue;
@@ -1665,16 +1664,7 @@ int dcn20_populate_dml_pipes_from_context(
if (timing->timing_3d_format ==
TIMING_3D_FORMAT_HW_FRAME_PACKING)
pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
pipes[pipe_cnt].pipe.dest.otg_inst =
res_ctx->pipe_ctx[i].stream_res.tg->inst;
-
- link = res_ctx->pipe_ctx[i].stream->link;
- if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) {
- pipes[pipe_cnt].dout.dp_lanes =
link->cur_link_settings.lane_count;
- } else if (link->verified_link_cap.lane_count !=
LANE_COUNT_UNKNOWN) {
- pipes[pipe_cnt].dout.dp_lanes =
link->verified_link_cap.lane_count;
- } else {
- /* Unknown link capabilities, so assume max */
- pipes[pipe_cnt].dout.dp_lanes = 4;
- }
+ pipes[pipe_cnt].dout.dp_lanes = 4;
pipes[pipe_cnt].pipe.dest.vtotal_min =
res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
pipes[pipe_cnt].pipe.dest.vtotal_max =
res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
--
2.20.1
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