please take care of .emit_ib_size member, otherwise it looks ok to me. -David
在 2019/6/20 8:02, Marek Olšák 写道: > From: Marek Olšák <[email protected]> > > Signed-off-by: Marek Olšák <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h | 3 ++- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 12 ++++++++++-- > 2 files changed, 12 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h > index dad2186f4ed5..df8a23554831 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h > @@ -24,21 +24,22 @@ > #ifndef __AMDGPU_GDS_H__ > #define __AMDGPU_GDS_H__ > > struct amdgpu_ring; > struct amdgpu_bo; > > struct amdgpu_gds { > uint32_t gds_size; > uint32_t gws_size; > uint32_t oa_size; > - uint32_t gds_compute_max_wave_id; > + uint32_t gds_compute_max_wave_id; > + uint32_t vgt_gs_max_wave_id; > }; > > struct amdgpu_gds_reg_offset { > uint32_t mem_base; > uint32_t mem_size; > uint32_t gws; > uint32_t oa; > }; > > #endif /* __AMDGPU_GDS_H__ */ > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 0090cba2d24d..75a34779a57c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -4213,20 +4213,29 @@ static void gfx_v10_0_ring_emit_hdp_flush(struct > amdgpu_ring *ring) > } > > static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, > struct amdgpu_job *job, > struct amdgpu_ib *ib, > uint32_t flags) > { > unsigned vmid = AMDGPU_JOB_GET_VMID(job); > u32 header, control = 0; > > + /* Prevent a hw deadlock due to a wave ID mismatch between ME and GDS. > + * This resets the wave ID counters. (needed by transform feedback) > + * TODO: This might only be needed on a VMID switch when we change > + * the GDS OA mapping, not sure. > + */ > + amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); > + amdgpu_ring_write(ring, mmVGT_GS_MAX_WAVE_ID); > + amdgpu_ring_write(ring, ring->adev->gds.vgt_gs_max_wave_id); > + > if (ib->flags & AMDGPU_IB_FLAG_CE) > header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); > else > header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); > > control |= ib->length_dw | (vmid << 24); > > if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { > control |= INDIRECT_BUFFER_PRE_ENB(1); > > @@ -5094,24 +5103,23 @@ static void gfx_v10_0_set_rlc_funcs(struct > amdgpu_device *adev) > default: > break; > } > } > > static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) > { > /* init asic gds info */ > switch (adev->asic_type) { > case CHIP_NAVI10: > - adev->gds.gds_size = 0x10000; > - break; > default: > adev->gds.gds_size = 0x10000; > + adev->gds.vgt_gs_max_wave_id = 0x3ff; > break; > } > > adev->gds.gws_size = 64; > adev->gds.oa_size = 16; > } > > static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct > amdgpu_device *adev, > u32 bitmap) > { _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
