Reviewed-by: Evan Quan <[email protected]>
> -----Original Message----- > From: amd-gfx <[email protected]> On Behalf Of > Wang, Kevin(Yang) > Sent: Thursday, July 11, 2019 9:41 PM > To: [email protected] > Cc: Wang, Kevin(Yang) <[email protected]>; Feng, Kenneth > <[email protected]> > Subject: [PATCH] drm/amd/powerplay: fix smu clock type change miss error > > in the smu module, use the smu_xxxclk type to identify the CLK type use > SMU_SCLK, SMU_MCLK to replace PP_SCLK, PP_MCLK. > > Change-Id: Ifa870aea38f043e1983f6f0560eed2ac070b68b7 > Signed-off-by: Kevin Wang <[email protected]> > --- > drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > index 1c15f02101fe..de6cc5d489cd 100644 > --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c > @@ -1386,8 +1386,8 @@ int smu_adjust_power_state_dynamic(struct > smu_context *smu, > &soc_mask); > if (ret) > return ret; > - smu_force_clk_levels(smu, PP_SCLK, 1 << > sclk_mask); > - smu_force_clk_levels(smu, PP_MCLK, 1 << > mclk_mask); > + smu_force_clk_levels(smu, SMU_SCLK, 1 << > sclk_mask); > + smu_force_clk_levels(smu, SMU_MCLK, 1 << > mclk_mask); > break; > > case AMD_DPM_FORCED_LEVEL_MANUAL: > -- > 2.22.0 > > _______________________________________________ > amd-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
