From: Nikola Cornij <[email protected]> [why] As a fail-safe, in case 'set FEC_READY' DPCD write fails, a HW shadow register should be cleared and the internal FEC stat should be set to 'not ready'. This is to make sure HW settings will be consistent with FEC_READY state on the RX.
Signed-off-by: Nikola Cornij <[email protected]> Reviewed-by: Joshua Aberback <[email protected]> Acked-by: Chris Park <[email protected]> Acked-by: Leo Li <[email protected]> --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 5c8e3318239c..b512fecae061 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -3174,6 +3174,8 @@ void dp_set_fec_ready(struct dc_link *link, bool ready) link_enc->funcs->fec_set_ready(link_enc, true); link->fec_state = dc_link_fec_ready; } else { + link->link_enc->funcs->fec_set_ready(link->link_enc, false); + link->fec_state = dc_link_fec_not_ready; dm_error("dpcd write failed to set fec_ready"); } } else if (link->fec_state == dc_link_fec_ready) { -- 2.22.0 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
