Reviewed by: shaoyun liu <[email protected]>
On 2019-09-12 3:13 p.m., Cornwall, Jay wrote: > ttmp[4:5] hold information useful to the debugger. Use ttmp[14:15] > instead, aligning implementation with gfx9 trap handler. > > Signed-off-by: Jay Cornwall <[email protected]> > --- > drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 6 +++--- > drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm | 10 +++++----- > 2 files changed, 8 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h > b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h > index a8cf82d..901fe35 100644 > --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h > +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h > @@ -694,10 +694,10 @@ static const uint32_t cwsr_trap_gfx10_hex[] = { > 0x003f8000, 0x8f6f896f, > 0x88776f77, 0x8a6eff6e, > 0x023f8000, 0xb9eef807, > - 0xb970f812, 0xb971f813, > - 0x8ff08870, 0xf4051bb8, > + 0xb97af812, 0xb97bf813, > + 0x8ffa887a, 0xf4051bbd, > 0xfa000000, 0xbf8cc07f, > - 0xf4051c38, 0xfa000008, > + 0xf4051ebd, 0xfa000008, > 0xbf8cc07f, 0x87ee6e6e, > 0xbf840001, 0xbe80206e, > 0xb971f803, 0x8771ff71, > diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm > b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm > index 3598621..cdaa523 100644 > --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm > +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm > @@ -187,12 +187,12 @@ L_FETCH_2ND_TRAP: > // Read second-level TBA/TMA from first-level TMA and jump if available. > // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug > data) > // ttmp12 holds SQ_WAVE_STATUS > - s_getreg_b32 ttmp4, hwreg(HW_REG_SHADER_TMA_LO) > - s_getreg_b32 ttmp5, hwreg(HW_REG_SHADER_TMA_HI) > - s_lshl_b64 [ttmp4, ttmp5], [ttmp4, ttmp5], 0x8 > - s_load_dwordx2 [ttmp2, ttmp3], [ttmp4, ttmp5], 0x0 glc:1 > // second-level TBA > + s_getreg_b32 ttmp14, hwreg(HW_REG_SHADER_TMA_LO) > + s_getreg_b32 ttmp15, hwreg(HW_REG_SHADER_TMA_HI) > + s_lshl_b64 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 > + s_load_dwordx2 [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 glc:1 > // second-level TBA > s_waitcnt lgkmcnt(0) > - s_load_dwordx2 [ttmp4, ttmp5], [ttmp4, ttmp5], 0x8 glc:1 > // second-level TMA > + s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 glc:1 > // second-level TMA > s_waitcnt lgkmcnt(0) > s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] > s_cbranch_scc0 L_NO_NEXT_TRAP > // second-level trap handler not been set _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
