Series is:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
________________________________
From: amd-gfx <amd-gfx-boun...@lists.freedesktop.org> on behalf of Tianci Yin
<tianci....@amd.com>
Sent: Wednesday, September 18, 2019 6:30 AM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Cc: Yin, Tianci (Rico) <tianci....@amd.com>; Zhang, Hawking
<hawking.zh...@amd.com>
Subject: [PATCH 2/2] drm/amdgpu/gfx10: update gfx golden settings for navi14
From: "Tianci.Yin" <tianci....@amd.com>
update registers: mmUTCL1_CTRL
Change-Id: I6df12555b72ba6faa926af8155b3f079e422a500
Signed-off-by: Tianci.Yin <tianci....@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 7901530d07f0..121824b47d02 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -161,7 +161,7 @@ static const struct soc15_reg_golden
golden_settings_gc_10_1_1[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff,
0xffffffff),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
- SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
};
static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
--
2.17.1
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