> -----Original Message-----
> From: amd-gfx <amd-gfx-boun...@lists.freedesktop.org> On Behalf Of
> Kenneth Feng
> Sent: Friday, November 8, 2019 1:43 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Feng, Kenneth <kenneth.f...@amd.com>
> Subject: [PATCH v2] drm/amd/powerplay: dynamically disable ds and ulv for
> compute
>
> This is to improve the performance in the compute mode
> for vega10. For example, the original performance for a rocm
> bandwidth test: 2G internal GPU copy, is about 99GB/s.
> With the idle power features disabled dynamically, the porformance
> is promoted to about 215GB/s.
>
> Signed-off-by: Kenneth Feng <kenneth.f...@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 7 +++
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 55
> ++++++++++++++++++++++
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 +
> 3 files changed, 64 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 0314476..bd35f65 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -969,6 +969,13 @@ static int pp_dpm_switch_power_profile(void *handle,
> workload = hwmgr->workload_setting[index];
> }
>
> + if (type == PP_SMC_POWER_PROFILE_COMPUTE &&
> + hwmgr->hwmgr_func-
> >disable_power_features_for_compute_performance)
> + if (hwmgr->hwmgr_func-
> >disable_power_features_for_compute_performance(hwmgr, en)) {
> + mutex_unlock(&hwmgr->smu_lock);
> + return -EINVAL;
> + }
[Quan, Evan] Coding style here seems a little weird. Other than this, the patch
is reviewed-by: Evan Quan <evan.q...@amd.com>
> +
> if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
> hwmgr->hwmgr_func->set_power_profile_mode(hwmgr,
> &workload, 0);
> mutex_unlock(&hwmgr->smu_lock);
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 4ea63a2..d3229c2 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -5263,6 +5263,59 @@ static int vega10_get_performance_level(struct
> pp_hwmgr *hwmgr, const struct pp_
> return 0;
> }
>
> +static int vega10_disable_power_features_for_compute_performance(struct
> pp_hwmgr *hwmgr, bool disable)
> +{
> + struct vega10_hwmgr *data = hwmgr->backend;
> + uint32_t feature_mask = 0;
> +
> + if (disable) {
> + feature_mask |= data->smu_features[GNLD_ULV].enabled ?
> + data->smu_features[GNLD_ULV].smu_feature_bitmap :
> 0;
> + feature_mask |= data-
> >smu_features[GNLD_DS_GFXCLK].enabled ?
> + data-
> >smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0;
> + feature_mask |= data-
> >smu_features[GNLD_DS_SOCCLK].enabled ?
> + data-
> >smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0;
> + feature_mask |= data-
> >smu_features[GNLD_DS_LCLK].enabled ?
> + data-
> >smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0;
> + feature_mask |= data-
> >smu_features[GNLD_DS_DCEFCLK].enabled ?
> + data-
> >smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0;
> + } else {
> + feature_mask |= (!data->smu_features[GNLD_ULV].enabled) ?
> + data->smu_features[GNLD_ULV].smu_feature_bitmap :
> 0;
> + feature_mask |= (!data-
> >smu_features[GNLD_DS_GFXCLK].enabled) ?
> + data-
> >smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0;
> + feature_mask |= (!data-
> >smu_features[GNLD_DS_SOCCLK].enabled) ?
> + data-
> >smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0;
> + feature_mask |= (!data-
> >smu_features[GNLD_DS_LCLK].enabled) ?
> + data-
> >smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0;
> + feature_mask |= (!data-
> >smu_features[GNLD_DS_DCEFCLK].enabled) ?
> + data-
> >smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0;
> + }
> +
> + if (feature_mask)
> +
> PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
> + !disable, feature_mask),
> + "enable/disable power features for compute
> performance Failed!",
> + return -EINVAL);
> +
> + if (disable) {
> + data->smu_features[GNLD_ULV].enabled = false;
> + data->smu_features[GNLD_DS_GFXCLK].enabled = false;
> + data->smu_features[GNLD_DS_SOCCLK].enabled = false;
> + data->smu_features[GNLD_DS_LCLK].enabled = false;
> + data->smu_features[GNLD_DS_DCEFCLK].enabled = false;
> + } else {
> + data->smu_features[GNLD_ULV].enabled = true;
> + data->smu_features[GNLD_DS_GFXCLK].enabled = true;
> + data->smu_features[GNLD_DS_SOCCLK].enabled = true;
> + data->smu_features[GNLD_DS_LCLK].enabled = true;
> + data->smu_features[GNLD_DS_DCEFCLK].enabled = true;
> + }
> +
> + return 0;
> +
> +}
> +
> static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
> .backend_init = vega10_hwmgr_backend_init,
> .backend_fini = vega10_hwmgr_backend_fini,
> @@ -5330,6 +5383,8 @@ static const struct pp_hwmgr_func
> vega10_hwmgr_funcs = {
> .get_ppfeature_status = vega10_get_ppfeature_status,
> .set_ppfeature_status = vega10_set_ppfeature_status,
> .set_mp1_state = vega10_set_mp1_state,
> + .disable_power_features_for_compute_performance =
> +
> vega10_disable_power_features_for_compute_performance,
> };
>
> int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 40403bc..af97767 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -357,6 +357,8 @@ struct pp_hwmgr_func {
> int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool aquire);
> int (*set_df_cstate)(struct pp_hwmgr *hwmgr, enum pp_df_cstate
> state);
> int (*set_xgmi_pstate)(struct pp_hwmgr *hwmgr, uint32_t pstate);
> + int (*disable_power_features_for_compute_performance)(struct
> pp_hwmgr *hwmgr,
> + bool disable);
> };
>
> struct pp_table_func {
> --
> 2.7.4
>
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