RE: [PATCH] drm/amdgpu: fix GFX10 missing CSIB set(v2)

[Liu, Monk]

Thanks, done

_____________________________________
Monk Liu|GPU Virtualization Team |AMD


-----Original Message-----
From: Zhang, Hawking <hawking.zh...@amd.com> 
Sent: Friday, November 29, 2019 5:29 PM
To: Liu, Monk <monk....@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Liu, Monk <monk....@amd.com>
Subject: RE: [PATCH] drm/amdgpu: fix GFX10 missing CSIB set(v2)

[AMD Public Use]

Please also drop the tlb flush. It is probably from code used for the emulation.
+               for (i = 0; i < adev->num_vmhubs; i++)
+                       amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);

With that fixed, the patch is
Reviewed-by: Hawking Zhang <hawking.zh...@amd.com>

Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-boun...@lists.freedesktop.org> On Behalf Of Monk Liu
Sent: 2019年11月29日 17:16
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Monk <monk....@amd.com>
Subject: [PATCH] drm/amdgpu: fix GFX10 missing CSIB set(v2)

still need to init csb even for SRIOV

v2:
drop init_pg() for gfx10 at all since
PG and GFX off feature will be fully controled by RLC and SMU fw for gfx10

Signed-off-by: Monk Liu <monk....@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 38 ++++++++++------------------------
 1 file changed, 11 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 53d11e9..a8eebc4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1766,22 +1766,6 @@ static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
        return 0;
 }
 
-static int gfx_v10_0_init_pg(struct amdgpu_device *adev) -{
-       int i;
-       int r;
-
-       r = gfx_v10_0_init_csb(adev);
-       if (r)
-               return r;
-
-       for (i = 0; i < adev->num_vmhubs; i++)
-               amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
-
-       /* TODO: init power gating */
-       return 0;
-}
-
 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)  {
        u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); @@ -1873,22 +1857,21 @@ 
static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)  static int 
gfx_v10_0_rlc_resume(struct amdgpu_device *adev)  {
        int r;
-
-       if (amdgpu_sriov_vf(adev))
-               return 0;
+       int i;
 
        if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+
                r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
                if (r)
                        return r;
 
-               r = gfx_v10_0_init_pg(adev);
-               if (r)
-                       return r;
+               gfx_v10_0_init_csb(adev);
 
-               /* enable RLC SRM */
-               gfx_v10_0_rlc_enable_srm(adev);
+               for (i = 0; i < adev->num_vmhubs; i++)
+                       amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
 
+               if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
+                       gfx_v10_0_rlc_enable_srm(adev);
        } else {
                adev->gfx.rlc.funcs->stop(adev);
 
@@ -1910,9 +1893,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device 
*adev)
                                return r;
                }
 
-               r = gfx_v10_0_init_pg(adev);
-               if (r)
-                       return r;
+               gfx_v10_0_init_csb(adev);
+
+               for (i = 0; i < adev->num_vmhubs; i++)
+                       amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
 
                adev->gfx.rlc.funcs->start(adev);
 
--
2.7.4

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