Series is Reviewed-by: Feifei Xu <Feifei [email protected]>
-----Original Message-----
From: Tianci Yin <[email protected]>
Sent: Wednesday, December 11, 2019 8:00 PM
To: [email protected]
Cc: Zhang, Hawking <[email protected]>; Xu, Feifei <[email protected]>;
Yuan, Xiaojie <[email protected]>; Long, Gang <[email protected]>; Li,
Pauline <[email protected]>; Yin, Tianci (Rico) <[email protected]>
Subject: [PATCH 2/2] drm/amdgpu/gfx10: update gfx golden settings for navi14
From: "Tianci.Yin" <[email protected]>
add registers: mmPA_SC_BINNER_TIMEOUT_COUNTER and mmPA_SC_ENHANCE_2
Change-Id: I1fc3fb481b2d9edc482a32497242a8be6cd6b8d7
Signed-off-by: Tianci.Yin <[email protected]>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index e5637a6efb05..8cdef79de9d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -162,8 +162,10 @@ static const struct soc15_reg_golden
golden_settings_gc_10_1_1[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff,
0x10000100),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER,
0xffffffff, 0x00000800),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000,
0x04440000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800,
0x00000820),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f,
0x00000000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f0000,
0x00070105),
--
2.17.1
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