Add defined peak sclk for navi12 peak profile mode.
Signed-off-by: Alex Deucher <[email protected]>
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 3 +++
drivers/gpu/drm/amd/powerplay/navi10_ppt.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index c33744a0d46b..106434689ec5 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1628,6 +1628,9 @@ static int navi10_set_peak_clock_by_device(struct
smu_context *smu)
break;
}
break;
+ case CHIP_NAVI12:
+ sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
+ break;
default:
ret = smu_get_dpm_level_count(smu, SMU_SCLK, &sclk_level);
if (ret)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
index ec03c7992f6d..f109401c2ee8 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
@@ -33,6 +33,8 @@
#define NAVI14_UMD_PSTATE_PEAK_XTX_GFXCLK (1717)
#define NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK (1448)
+#define NAVI12_UMD_PSTATE_PEAK_GFXCLK (1100)
+
#define NAVI10_VOLTAGE_SCALE (4)
#define smnPCIE_LC_SPEED_CNTL 0x11140290
--
2.24.1
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