Both are needed on vega20 and arcturus chip.
Signed-off-by: Guchun Chen <[email protected]>
---
drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h | 2 ++
drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_2_offset.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h
index 043aa695d63f..0d6b594be775 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h
@@ -27,5 +27,7 @@
#define mmUMCCH0_0_EccErrCnt_BASE_IDX
0
#define mmMCA_UMC_UMC0_MCUMC_STATUST0
0x03c2
#define mmMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX
0
+#define mmMCA_UMC_UMC0_MCUMC_ADDRT0
0x03c4
+#define mmMCA_UMC_UMC0_MCUMC_ADDRT0_BASE_IDX
0
#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_2_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_2_offset.h
index 03be415e9555..ce005c674a18 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_2_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_2_offset.h
@@ -27,5 +27,7 @@
#define mmUMCCH0_0_EccErrCnt_ARCT_BASE_IDX 1
#define mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT 0x03c2
#define mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT_BASE_IDX 1
+#define mmMCA_UMC_UMC0_MCUMC_ADDRT0_ARCT 0x03c4
+#define mmMCA_UMC_UMC0_MCUMC_ADDRT0_ARCT_BASE_IDX 1
#endif
--
2.17.1
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