Add direct SRAM read and write MACRO for vcn2.5
Signed-off-by: James Zhu <[email protected]>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 26c6623..d3d75ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -127,6 +127,24 @@
}
\
} while (0)
+#define RREG32_SOC15_DPG_MODE_2_5(inst_idx, offset, mask_en)
\
+ ({
\
+ WREG32_SOC15(VCN, inst, mmUVD_DPG_LMA_CTL,
\
+ (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT |
\
+ mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT |
\
+ offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT));
\
+ RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA);
\
+ })
+
+#define WREG32_SOC15_DPG_MODE_2_5(inst_idx, offset, value, mask_en, indirect)
\
+ do {
\
+ WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA, value);
\
+ WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL,
\
+ (0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT |
\
+ mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT |
\
+ offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT));
\
+ } while (0)
+
enum engine_status_constants {
UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0,
--
2.7.4
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