From: Nicholas Kazlauskas <nicholas.kazlaus...@amd.com>

[Why]
Under some hardware initialization sequences the fb base/fb offset
provided can be zero or hardwareinit can happen too late.

We want to ensure that we always have the correct fb_base/fb_offset
when performing DMCUB hardware initialization so we can do DMCUB
command table offloading during first dc hardware init.

[How]
Read from the DCN registers. VBIOS already filled these in for us.

Change-Id: Iea84fd8bda3bff750e6aada75175711c01c6a256
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlaus...@amd.com>
Reviewed-by: Wesley Chalmers <wesley.chalm...@amd.com>
Acked-by: Bhawanpreet Lakha <bhawanpreet.la...@amd.com>
IP-reviewed-by: Nicholas Kazlauskas <nicholas.kazlaus...@amd.com>
---
 .../gpu/drm/amd/display/dmub/inc/dmub_srv.h   |  2 ++
 .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 21 +++++++++++++++++--
 .../gpu/drm/amd/display/dmub/src/dmub_dcn20.h |  8 +++++--
 3 files changed, 27 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h 
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
index 8e23a7017588..287fb9a36a64 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
@@ -231,6 +231,8 @@ struct dmub_srv_base_funcs {
 struct dmub_srv_hw_funcs {
        /* private: internal use only */
 
+       void (*init)(struct dmub_srv *dmub);
+
        void (*reset)(struct dmub_srv *dmub);
 
        void (*reset_release)(struct dmub_srv *dmub);
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c 
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
index cd51c6138894..9229012b93e2 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
@@ -54,6 +54,19 @@ const struct dmub_srv_common_regs dmub_srv_dcn20_regs = {
 
 /* Shared functions. */
 
+static void dmub_dcn20_get_fb_base_offset(struct dmub_srv *dmub,
+                                         uint64_t *fb_base,
+                                         uint64_t *fb_offset)
+{
+       uint32_t tmp;
+
+       REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
+       *fb_base = (uint64_t)tmp << 24;
+
+       REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
+       *fb_offset = (uint64_t)tmp << 24;
+}
+
 static inline void dmub_dcn20_translate_addr(const union dmub_addr *addr_in,
                                             uint64_t fb_base,
                                             uint64_t fb_offset,
@@ -82,7 +95,9 @@ void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,
                              const struct dmub_window *cw1)
 {
        union dmub_addr offset;
-       uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset;
+       uint64_t fb_base, fb_offset;
+
+       dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset);
 
        REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
        REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x3,
@@ -118,7 +133,9 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
                              const struct dmub_window *cw6)
 {
        union dmub_addr offset;
-       uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset;
+       uint64_t fb_base, fb_offset;
+
+       dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset);
 
        dmub_dcn20_translate_addr(&cw2->offset, fb_base, fb_offset, &offset);
 
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h 
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
index 53bfd4da69ad..04b0fa13153d 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
@@ -92,7 +92,9 @@ struct dmub_srv;
        DMUB_SR(DMCUB_SCRATCH14) \
        DMUB_SR(DMCUB_SCRATCH15) \
        DMUB_SR(CC_DC_PIPE_DIS) \
-       DMUB_SR(MMHUBBUB_SOFT_RESET)
+       DMUB_SR(MMHUBBUB_SOFT_RESET) \
+       DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
+       DMUB_SR(DCN_VM_FB_OFFSET)
 
 #define DMUB_COMMON_FIELDS() \
        DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \
@@ -121,7 +123,9 @@ struct dmub_srv;
        DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \
        DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \
        DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \
-       DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET)
+       DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \
+       DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \
+       DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET)
 
 struct dmub_srv_common_reg_offset {
 #define DMUB_SR(reg) uint32_t reg;
-- 
2.17.1

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