Thanks.

Reviewed-by: Bhawanpreet Lakha <[email protected]>

On 2020-02-19 9:24 a.m., Alex Deucher wrote:
Use the existence of the workqueue itself to determine when to
enable HDCP features rather than sprinkling asic checks all over
the code.  Also add a check for the existence of the hdcp
workqueue in the irq handling on the off chance we get and HPD
RX interrupt with the CP bit set.  This avoids a crash if
the driver doesn't support HDCP for a particular asic.

Fixes: 96a3b32e67236f ("drm/amd/display: only enable HDCP for DCN+")
Bug: 
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.kernel.org%2Fshow_bug.cgi%3Fid%3D206519&amp;data=02%7C01%7Cbhawanpreet.lakha%40amd.com%7C0bb0c7154e6946e09b0c08d7b547766c%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637177190908488608&amp;sdata=AQqpGAH86XJj%2FtdLOWgWQchwffQYW2ob5aSXzJiaQJo%3D&amp;reserved=0
Signed-off-by: Alex Deucher <[email protected]>
---
  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++++++----
  1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f7d541030698..4cb3eb7c6745 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1961,7 +1961,7 @@ static void handle_hpd_irq(void *param)
        mutex_lock(&aconnector->hpd_lock);
#ifdef CONFIG_DRM_AMD_DC_HDCP
-       if (adev->asic_type >= CHIP_RAVEN)
+       if (adev->dm.hdcp_workqueue)
                hdcp_reset_display(adev->dm.hdcp_workqueue, 
aconnector->dc_link->link_index);
  #endif
        if (aconnector->fake_enable)
@@ -2138,8 +2138,10 @@ static void handle_hpd_rx_irq(void *param)
                }
        }
  #ifdef CONFIG_DRM_AMD_DC_HDCP
-       if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ)
-               hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  
aconnector->base.index);
+           if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
+                   if (adev->dm.hdcp_workqueue)
+                           hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  
aconnector->base.index);
+           }
  #endif
        if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
            (dc_link->type == dc_connection_mst_branch))
@@ -5836,7 +5838,7 @@ void amdgpu_dm_connector_init_helper(struct 
amdgpu_display_manager *dm,
                drm_connector_attach_vrr_capable_property(
                        &aconnector->base);
  #ifdef CONFIG_DRM_AMD_DC_HDCP
-               if (adev->asic_type >= CHIP_RAVEN)
+               if (adev->dm.hdcp_workqueue)
                        
drm_connector_attach_content_protection_property(&aconnector->base, true);
  #endif
        }
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