On 03/04, Kazlauskas, Nicholas wrote:
> On 2020-03-03 6:27 p.m., Rodrigo Siqueira wrote:
> > From: Martin Leung <martin.le...@amd.com>
> >
> > [why]
> > nv14 previously inherited soc bb from generic dcn 2, did not match
> > watermark values according to memory team
> >
> > [how]
> > add nv14 specific soc bb: copy nv2 generic that it was
> > using from before, but changed num channels to 8
> >
> > Signed-off-by: Martin Leung <martin.le...@amd.com>
> > Reviewed-by: Jun Lei <jun....@amd.com>
> > Acked-by: Rodrigo Siqueira <rodrigo.sique...@amd.com>
> > ---
> > .../drm/amd/display/dc/dcn20/dcn20_resource.c | 113 +++++++++++++++++-
> > 1 file changed, 112 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> > b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> > index c629a7b45f56..c8b85f62ae95 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> > @@ -337,6 +337,117 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
> > .use_urgent_burst_bw = 0
> > };
> > +struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {
> > + .clock_limits = {
> > + {
> > + .state = 0,
> > + .dcfclk_mhz = 560.0,
> > + .fabricclk_mhz = 560.0,
> > + .dispclk_mhz = 513.0,
> > + .dppclk_mhz = 513.0,
> > + .phyclk_mhz = 540.0,
> > + .socclk_mhz = 560.0,
> > + .dscclk_mhz = 171.0,
> > + .dram_speed_mts = 8960.0,
> > + },
> > + {
> > + .state = 1,
> > + .dcfclk_mhz = 694.0,
> > + .fabricclk_mhz = 694.0,
> > + .dispclk_mhz = 642.0,
> > + .dppclk_mhz = 642.0,
> > + .phyclk_mhz = 600.0,
> > + .socclk_mhz = 694.0,
> > + .dscclk_mhz = 214.0,
> > + .dram_speed_mts = 11104.0,
> > + },
> > + {
> > + .state = 2,
> > + .dcfclk_mhz = 875.0,
> > + .fabricclk_mhz = 875.0,
> > + .dispclk_mhz = 734.0,
> > + .dppclk_mhz = 734.0,
> > + .phyclk_mhz = 810.0,
> > + .socclk_mhz = 875.0,
> > + .dscclk_mhz = 245.0,
> > + .dram_speed_mts = 14000.0,
> > + },
> > + {
> > + .state = 3,
> > + .dcfclk_mhz = 1000.0,
> > + .fabricclk_mhz = 1000.0,
> > + .dispclk_mhz = 1100.0,
> > + .dppclk_mhz = 1100.0,
> > + .phyclk_mhz = 810.0,
> > + .socclk_mhz = 1000.0,
> > + .dscclk_mhz = 367.0,
> > + .dram_speed_mts = 16000.0,
> > + },
> > + {
> > + .state = 4,
> > + .dcfclk_mhz = 1200.0,
> > + .fabricclk_mhz = 1200.0,
> > + .dispclk_mhz = 1284.0,
> > + .dppclk_mhz = 1284.0,
> > + .phyclk_mhz = 810.0,
> > + .socclk_mhz = 1200.0,
> > + .dscclk_mhz = 428.0,
> > + .dram_speed_mts = 16000.0,
> > + },
> > + /*Extra state, no dispclk ramping*/
> > + {
> > + .state = 5,
> > + .dcfclk_mhz = 1200.0,
> > + .fabricclk_mhz = 1200.0,
> > + .dispclk_mhz = 1284.0,
> > + .dppclk_mhz = 1284.0,
> > + .phyclk_mhz = 810.0,
> > + .socclk_mhz = 1200.0,
> > + .dscclk_mhz = 428.0,
> > + .dram_speed_mts = 16000.0,
> > + },
> > + },
> > + .num_states = 5,
> > + .sr_exit_time_us = 8.6,
> > + .sr_enter_plus_exit_time_us = 10.9,
> > + .urgent_latency_us = 4.0,
> > + .urgent_latency_pixel_data_only_us = 4.0,
> > + .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
> > + .urgent_latency_vm_data_only_us = 4.0,
> > + .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
> > + .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
> > + .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
> > + .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
> > + .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
> > + .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
> > + .max_avg_sdp_bw_use_normal_percent = 40.0,
> > + .max_avg_dram_bw_use_normal_percent = 40.0,
> > + .writeback_latency_us = 12.0,
> > + .ideal_dram_bw_after_urgent_percent = 40.0,
> > + .max_request_size_bytes = 256,
> > + .dram_channel_width_bytes = 2,
> > + .fabric_datapath_to_dcn_data_return_bytes = 64,
> > + .dcn_downspread_percent = 0.5,
> > + .downspread_percent = 0.38,
> > + .dram_page_open_time_ns = 50.0,
> > + .dram_rw_turnaround_time_ns = 17.5,
> > + .dram_return_buffer_per_channel_bytes = 8192,
> > + .round_trip_ping_latency_dcfclk_cycles = 131,
> > + .urgent_out_of_order_return_per_channel_bytes = 256,
> > + .channel_interleave_bytes = 256,
> > + .num_banks = 8,
> > + .num_chans = 8,
> > + .vmm_page_size_bytes = 4096,
> > + .dram_clock_change_latency_us = 404.0,
> > + .dummy_pstate_latency_us = 5.0,
> > + .writeback_dram_clock_change_latency_us = 23.0,
> > + .return_bus_width_bytes = 64,
> > + .dispclk_dppclk_vco_speed_mhz = 3850,
> > + .xfc_bus_transport_time_us = 20,
> > + .xfc_xbuf_latency_tolerance_us = 4,
> > + .use_urgent_burst_bw = 0
> > +};
> > +
> > struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
> > #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
> > @@ -3298,7 +3409,7 @@ static struct _vcs_dpi_soc_bounding_box_st
> > *get_asic_rev_soc_bb(
> > uint32_t hw_internal_rev)
> > {
> > if (ASICREV_IS_NAVI12_P(hw_internal_rev))
> > - return &dcn2_0_nv12_soc;
> > + return &dcn2_0_nv14_soc;
>
> Are you sure this is correct? Shouldn't be checking that the ASICREV is
> Navi14 here, not Navi12?
Nice catch! I correct it to:
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -3408,9 +3408,12 @@ void dcn20_patch_bounding_box(struct dc *dc, struct
_vcs_dpi_soc_bounding_box_st
static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
uint32_t hw_internal_rev)
{
- if (ASICREV_IS_NAVI12_P(hw_internal_rev))
+ if (ASICREV_IS_NAVI14_M(hw_internal_rev))
return &dcn2_0_nv14_soc;
+ if (ASICREV_IS_NAVI12_P(hw_internal_rev))
+ return &dcn2_0_nv12_soc;
+
return &dcn2_0_soc;
}
Thanks!
> Nicholas Kazlauskas
>
> > return &dcn2_0_soc;
> > }
> >
>
--
Rodrigo Siqueira
https://siqueira.tech
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