[AMD Official Use Only - Internal Distribution Only]
I see. So it's the following programming that is in risk to corrupt data for
other instances.
/* clear umc status */
WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);
For error injection, everytime it should just have one instance had the error
status record. Therefore, it make sense to me that we only clear the status
register once. As discussed, we shall also follow up with umc team on the
potential issue with index mode programming.
Please also add some comments in code for this unexpected behavior that we
shall follow up. Other than that, the patch is
Reviewed-by: Hawking Zhang <[email protected]>
Regards,
Hawking
From: Clements, John <[email protected]>
Sent: Thursday, March 5, 2020 18:19
To: Zhang, Hawking <[email protected]>; [email protected]; Li,
Dennis <[email protected]>; Zhou1, Tao <[email protected]>; Chen, Guchun
<[email protected]>
Subject: RE: [PATCH] drm/amdgpu: update page retirement sequence
[AMD Official Use Only - Internal Distribution Only]
In the original sequence, if the key bits are not set in the mca_status, the
page retirement will not happen and the status register will be cleared.
If there is a UMC UE, that register will be cleared erroneously 31 times.
If MCA Status == 0 already from the beginning there is no reason to press
forward with the rest of the checks and clear the register.
From: Zhang, Hawking <[email protected]<mailto:[email protected]>>
Sent: Thursday, March 5, 2020 5:56 PM
To: Clements, John <[email protected]<mailto:[email protected]>>;
[email protected]<mailto:[email protected]>; Li, Dennis
<[email protected]<mailto:[email protected]>>; Zhou1, Tao
<[email protected]<mailto:[email protected]>>; Chen, Guchun
<[email protected]<mailto:[email protected]>>
Subject: RE: [PATCH] drm/amdgpu: update page retirement sequence
[AMD Official Use Only - Internal Distribution Only]
Hi John,
Can you please explain more on the differences between (a). exit immediately
when mca_status is 0 and (b). exit when some of critical field in mca_status is
0?
Regards,
Hawking
From: Clements, John <[email protected]<mailto:[email protected]>>
Sent: Thursday, March 5, 2020 17:40
To: [email protected]<mailto:[email protected]>; Zhang,
Hawking <[email protected]<mailto:[email protected]>>; Li, Dennis
<[email protected]<mailto:[email protected]>>; Zhou1, Tao
<[email protected]<mailto:[email protected]>>; Chen, Guchun
<[email protected]<mailto:[email protected]>>
Subject: [PATCH] drm/amdgpu: update page retirement sequence
[AMD Official Use Only - Internal Distribution Only]
check UMC status and exit prior to making and erroneus register access
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