[AMD Official Use Only - Internal Distribution Only] Reviewed-by: Hawking Zhang <[email protected]>
Regards, Hawking -----Original Message----- From: Dennis Li <[email protected]> Sent: Monday, March 23, 2020 13:11 To: [email protected]; Deucher, Alexander <[email protected]>; Zhou1, Tao <[email protected]>; Zhang, Hawking <[email protected]>; Chen, Guchun <[email protected]> Cc: Li, Dennis <[email protected]> Subject: [PATCH] drm/amdgpu: fix the coverage issue to clear ArcVPGRs Set ComputePGMRSRC1.VGPRS as 0x3f to clear all ArcVGPRs. Change-Id: I296c3a162c0d5c7b84d4b48dc2002340a5c22e2a Signed-off-by: Dennis Li <[email protected]> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c old mode 100644 new mode 100755 index 324838baa71c..44fb64460c1f --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4264,7 +4264,7 @@ static const struct soc15_reg_entry vgpr_init_regs_arcturus[] = { { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 }, { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, - { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x81 }, + { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0xbf }, { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */ { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, -- 2.17.1 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
