Hi @Koenig, Christian<mailto:christian.koe...@amd.com> & Marek
I still have some concerns regarding Marek’s patch, correct me if I’m wrong See that Marek put a SDMA_OP_GCR_REQ before emitting IB, to make sure SDMA won’t get stale cache data during the IB execution. But that “SDMA_OP_GCR_REQ” only invalidate/flush the GFXHUB’s G2LC cache right ? what if the memory is changed by MM or CPU (out side of GFXHUB) ? Can this “ SDMA_OP_GCR_REQ” force MMHUB or even CPU to flush their operation result from their cache to memory ?? Besides, with my understanding the “EOP” of gfx ring is doing the thing of “invalidate/flush” L2 cache upon a fence signaled, so what we should do on SDMA5 is to insert this “SDMA_OP_GCR_REQ” Right before thee “emit_fence” of SDMA (this is what windows KMD do) thanks _____________________________________ Monk Liu|GPU Virtualization Team |AMD [sig-cloud-gpu] From: amd-gfx <amd-gfx-boun...@lists.freedesktop.org> On Behalf Of Marek Ol?ák Sent: Saturday, April 25, 2020 4:52 PM To: amd-gfx mailing list <amd-gfx@lists.freedesktop.org> Subject: drm/amdgpu: invalidate L2 before SDMA IBs (on gfx10) This should fix SDMA hangs on gfx10. Marek
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