[AMD Official Use Only - Internal Distribution Only] I will do that instead. Thanks for the recommendation!
Kent > -----Original Message----- > From: Alex Deucher <[email protected]> > Sent: Tuesday, May 5, 2020 3:20 PM > To: Russell, Kent <[email protected]> > Cc: amd-gfx list <[email protected]> > Subject: Re: [PATCH] Revert "Revert "drm/amdgpu: use the BAR if possible in > amdgpu_device_vram_access v2"" > > On Tue, May 5, 2020 at 2:57 PM Kent Russell <[email protected]> wrote: > > > > This reverts commit e71391880aa72709fac53f98d96a2d4e8875b9fa. > > > > The RAS issue at the base of this problem appears to have been > > addressed > > > > Signed-off-by: Kent Russell <[email protected]> > > Change-Id: I338a985e19cae8e103bd44b0f238314e9460d396 > > Would probably be cleaner to just re-apply the original patch with an > additional note in the commit than to revert the revert. Either way: > Acked-by: Alex Deucher <[email protected]> > > > --- > > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 26 > > ++++++++++++++++++++++ > > 1 file changed, 26 insertions(+) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > > index caa38e7d502e..bf302c799832 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > > @@ -255,6 +255,32 @@ void amdgpu_device_vram_access(struct > amdgpu_device *adev, loff_t pos, > > uint32_t hi = ~0; > > uint64_t last; > > > > + > > +#ifdef CONFIG_64BIT > > + last = min(pos + size, adev->gmc.visible_vram_size); > > + if (last > pos) { > > + void __iomem *addr = adev->mman.aper_base_kaddr + pos; > > + size_t count = last - pos; > > + > > + if (write) { > > + memcpy_toio(addr, buf, count); > > + mb(); > > + amdgpu_asic_flush_hdp(adev, NULL); > > + } else { > > + amdgpu_asic_invalidate_hdp(adev, NULL); > > + mb(); > > + memcpy_fromio(buf, addr, count); > > + } > > + > > + if (count == size) > > + return; > > + > > + pos += count; > > + buf += count / 4; > > + size -= count; > > + } > > +#endif > > + > > spin_lock_irqsave(&adev->mmio_idx_lock, flags); > > for (last = pos + size; pos < last; pos += 4) { > > uint32_t tmp = pos >> 31; > > -- > > 2.17.1 > > > > _______________________________________________ > > amd-gfx mailing list > > [email protected] > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist > > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd- > gfx&data=02%7C01%7Cke > > > nt.russell%40amd.com%7C95de921aa6dc453f4f8f08d7f12963e5%7C3dd8961f > e488 > > > 4e608e11a82d994e183d%7C0%7C0%7C637243032382055171&sdata=B4 > 05lc1cG% > > 2Bvgl36OKNnkgTBHHweB%2BizscB%2BJZxtilx8%3D&reserved=0 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
