The 2 patches are:
Reviewed-by: Leo Liu <leo....@amd.com>
-----Original Message-----
From: amd-gfx <amd-gfx-boun...@lists.freedesktop.org> On Behalf Of James Zhu
Sent: May 19, 2020 10:42 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, James <james....@amd.com>
Subject: [PATCH 2/2] drm/amdgpu/vcn2.5: Remove old DPG workaround
SCRATCH2 is used to keep decode wptr as a workaround which fix a hardware DPG
decode wptr update bug for
vcn2.5 beforehand.
Signed-off-by: James Zhu <james....@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 34ed906..3c6eafb 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -1453,11 +1453,6 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device
*adev,
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2,
lower_32_bits(ring->wptr));
fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
- fw_shared->multi_queue.decode_queue_mode |=
FW_QUEUE_RING_RESET;
- WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,
- RREG32_SOC15(VCN, inst_idx,
mmUVD_SCRATCH2) & 0x7FFFFFFF);
- fw_shared->multi_queue.decode_queue_mode &=
~FW_QUEUE_RING_RESET;
-
/* Unstall DPG */
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx,
mmUVD_POWER_STATUS),
0,
~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
@@ -1519,10 +1514,6 @@ static void vcn_v2_5_dec_ring_set_wptr(struct
amdgpu_ring *ring) {
struct amdgpu_device *adev = ring->adev;
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
- WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2,
- lower_32_bits(ring->wptr) | 0x80000000);
-
if (ring->use_doorbell) {
adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
--
2.7.4
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