Re: [PATCH] drm/amdgpu/display: fix build without CONFIG_DRM_AMD_DC_DCN3_0

[Kazlauskas, Nicholas]

On 2020-06-03 2:00 p.m., Alex Deucher wrote:

Need to guard some new DCN3.0 stuff.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlaus...@amd.com>

Thanks!

Nicholas Kazlauskas

---
  drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 5 ++++-
  1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index 43d0b4e53b5d..2972392f9788 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -288,13 +288,16 @@ void optc1_program_timing(
        if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || 
optc1->opp_count == 2)
                h_div = H_TIMING_DIV_BY2;

+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)

        if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) {
                if (optc1->opp_count == 4)
                        h_div = H_TIMING_DIV_BY4;

REG_UPDATE(OTG_H_TIMING_CNTL,

                OTG_H_TIMING_DIV_MODE, h_div);
-       } else {
+       } else
+#endif
+       {
                REG_UPDATE(OTG_H_TIMING_CNTL,
                OTG_H_TIMING_DIV_BY2, h_div);
        }

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx